First dataflow_test is added.

Author: shtaxxx

pyverilog/dataflow/dataflow.py

@@ -522,7 +522,7 @@ def __init__(self,name,termtype=(),msb=None,lsb=None,lenmsb=None,lenlsb=None):
     def __repr__(self):
         return str(self.name)
     def tostr(self):
-        ret = '(Term name:' + str(self.name) + ' type:' + str(self.termtype)
+        ret = '(Term name:' + str(self.name) + ' type:' + str(sorted(self.termtype, key=lambda x:str(x)))
         if self.msb is not None: ret += ' msb:' + self.msb.tostr()
         if self.lsb is not None: ret += ' lsb:' + self.lsb.tostr()
         if self.lenmsb is not None: ret += ' lenmsb:' + self.lenmsb.tostr()

pyverilog/dataflow/dataflow_analyzer.py

@@ -137,13 +137,13 @@ def showVersion():
 
     directives = verilogdataflowanalyzer.get_directives()
     print('Directive:')
-    for dr in directives:
+    for dr in sorted(directives, key=lambda x:str(x)):
         print(dr)
 
     instances = verilogdataflowanalyzer.getInstances()
     print('Instance:')
-    for ins in instances:
-        print(ins)
+    for module, instname in sorted(instances, key=lambda x:str(x[1])):
+        print((module, instname))
 
     if options.nobind:
         print('Signal:')
@@ -159,11 +159,11 @@ def showVersion():
     else:
         terms = verilogdataflowanalyzer.getTerms()
         print('Term:')
-        for tk, tv in sorted(terms.items(), key=lambda x:len(x[0])):
+        for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
             print(tv.tostr())
 
         binddict = verilogdataflowanalyzer.getBinddict()
         print('Bind:')
-        for bk, bv in sorted(binddict.items(), key=lambda x:len(x[0])):
+        for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
             for bvi in bv:
                 print(bvi.tostr())

tests/dataflow_test/Makefile

@@ -0,0 +1,19 @@
+TEST=*.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

tests/dataflow_test/pyverilog

@@ -0,0 +1 @@
+../../pyverilog

tests/dataflow_test/test_led.py

@@ -0,0 +1,72 @@
+import os
+import sys
+from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+
+codedir = '../../testcode/'
+
+expected = """\
+Directive:
+Instance:
+(led, 'led')
+Term:
+(Term name:led.CLK type:['Input'] msb:(IntConst 0) lsb:(IntConst 0))
+(Term name:led.LED type:['Output', 'Reg'] msb:(IntConst 7) lsb:(IntConst 0))
+(Term name:led.RST type:['Input'] msb:(IntConst 0) lsb:(IntConst 0))
+(Term name:led.STEP type:['Parameter'] msb:'d31 lsb:'d0)
+(Term name:led.count type:['Reg'] msb:(IntConst 31) lsb:(IntConst 0))
+Bind:
+(Bind dest:led.LED tree:(Branch Cond:(Terminal led.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal led.count),(Operator Minus Next:(Terminal led.STEP),(IntConst 1))) True:(Operator Plus Next:(Terminal led.LED),(IntConst 1)))))
+(Bind dest:led.STEP tree:(IntConst 10))
+(Bind dest:led.count tree:(Branch Cond:(Terminal led.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal led.count),(Operator Minus Next:(Terminal led.STEP),(IntConst 1))) True:(IntConst 0) False:(Operator Plus Next:(Terminal led.count),(IntConst 1)))))
+"""
+
+def test():
+    filelist = [codedir + 'led.v']
+    topmodule = 'led'
+    noreorder = False
+    nobind = False
+    include = None
+    define = None
+    
+    analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
+                                       noreorder=noreorder,
+                                       nobind=nobind,
+                                       preprocess_include=include,
+                                       preprocess_define=define)
+    analyzer.generate()
+
+    directives = analyzer.get_directives()
+    instances = analyzer.getInstances()
+    terms = analyzer.getTerms()
+    binddict = analyzer.getBinddict()
+
+    output = []
+    
+    output.append('Directive:\n')
+    for dr in sorted(directives, key=lambda x:str(x)):
+        output.append(str(dr))
+        output.append('\n')
+
+    output.append('Instance:\n')
+    for module, instname in sorted(instances, key=lambda x:str(x[1])):
+        output.append(str((module, instname)))
+        output.append('\n')
+
+    output.append('Term:\n')
+    for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
+        output.append(tv.tostr())
+        output.append('\n')
+        
+    output.append('Bind:\n')
+    for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
+        for bvi in bv:
+            output.append(bvi.tostr())
+            output.append('\n')
+            
+    rslt = ''.join(output)
+
+    print(rslt)
+    assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()

tests/parser_test/pyverilog

@@ -0,0 +1 @@
+../../pyverilog/

tests/parser_test/test_delay.py

@@ -88,4 +88,8 @@ def test():
 
     rslt = output.getvalue()
 
+    print(rslt)
     assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()

tests/parser_test/test_escape.py

@@ -123,4 +123,8 @@ def test():
 
     rslt = output.getvalue()
 
+    print(rslt)
     assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()

tests/parser_test/test_instance_array.py

@@ -229,4 +229,8 @@ def test():
 
     rslt = output.getvalue()
 
+    print(rslt)
     assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()

tests/parser_test/test_led.py tests/parser_test/test_led_main.pytests/parser_test/test_led.py renamed to tests/parser_test/test_led_main.py

@@ -142,4 +142,8 @@ def test():
 
     rslt = output.getvalue()
 
+    print(rslt)
     assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()