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pytest modules for preprocessor and parser are added.
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14 files changed

+477
-42
lines changed

14 files changed

+477
-42
lines changed

‎pyverilog/vparser/lexer.py‎

Lines changed: 57 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,10 @@
11
#-------------------------------------------------------------------------------
22
# lexer.py
33
#
4-
# Lexical analyzer
4+
# Verilog Lexical Analyzer
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7-
#
8-
# edited by ryosuke fukatani
9-
#
7+
# Edited by ryosuke fukatani
108
# License: Apache 2.0
119
#-------------------------------------------------------------------------------
1210

@@ -265,20 +263,66 @@ def _find_tok_column(self, token):
265263
def _make_tok_location(self, token):
266264
return (token.lineno, self._find_tok_column(token))
267265

268-
if __name__ == '__main__':
266+
#-------------------------------------------------------------------------------
267+
def dump_tokens(text):
269268
def my_error_func(msg, a, b):
270269
sys.write(msg + "\n")
271270
sys.exit()
272-
273-
filename = '../testcode/test.v'
274-
text = open(filename, 'r').read()
275-
276-
lexer = VerilogLexer(error_func = my_error_func)
271+
272+
lexer = VerilogLexer(error_func=my_error_func)
277273
lexer.build()
278274
lexer.input(text)
279275

276+
ret = []
277+
280278
# Tokenize
281-
while 1:
279+
while True:
282280
tok = lexer.token()
283-
if not tok: break # No more input
284-
print (tok.value, tok.type, tok.lineno, lexer.filename, tok.lexpos)
281+
if not tok: break # No more input
282+
ret.append("%s %s %d %s %d\n" %
283+
(tok.value, tok.type, tok.lineno, lexer.filename, tok.lexpos))
284+
285+
return ''.join(ret)
286+
287+
#-------------------------------------------------------------------------------
288+
if __name__ == '__main__':
289+
import pyverilog.utils.version
290+
from pyverilog.vparser.preprocessor import preprocess
291+
from optparse import OptionParser
292+
293+
INFO = "Verilog Preprocessor"
294+
VERSION = pyverilog.utils.version.VERSION
295+
USAGE = "Usage: python preprocessor.py file ..."
296+
297+
def showVersion():
298+
print(INFO)
299+
print(VERSION)
300+
print(USAGE)
301+
sys.exit()
302+
303+
optparser = OptionParser()
304+
optparser.add_option("-v","--version",action="store_true",dest="showversion",
305+
default=False,help="Show the version")
306+
optparser.add_option("-I","--include",dest="include",action="append",
307+
default=[],help="Include path")
308+
optparser.add_option("-D",dest="define",action="append",
309+
default=[],help="Macro Definition")
310+
(options, args) = optparser.parse_args()
311+
312+
filelist = args
313+
if options.showversion:
314+
showVersion()
315+
316+
for f in filelist:
317+
if not os.path.exists(f): raise IOError("file not found: " + f)
318+
319+
if len(filelist) == 0:
320+
showVersion()
321+
322+
text = preprocess(filelist,
323+
preprocess_include=options.include,
324+
preprocess_define=options.define)
325+
326+
dump = dump_tokens(text)
327+
328+
print(dump)

‎pyverilog/vparser/parser.py‎

Lines changed: 15 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1739,20 +1739,7 @@ def p_error(self, p):
17391739
else:
17401740
self._parse_error('At end of input', '')
17411741

1742-
################################################################################
1743-
def preprocess(filelist, preprocess_output='preprocess.output'):
1744-
pre = VerilogPreprocessor(filelist, preprocess_output)
1745-
pre.preprocess()
1746-
text = open(preprocess_output).read()
1747-
os.remove(preprocess_output)
1748-
return text
1749-
1750-
def parse(filelist, preprocess_output='preprocess.output', debug=0):
1751-
text = preprocess(filelist, preprocess_output)
1752-
parser = VerilogParser()
1753-
ast = parser.parse(text, debug=debug)
1754-
return ast
1755-
1742+
#-------------------------------------------------------------------------------
17561743
class VerilogCodeParser(object):
17571744
def __init__(self, filelist, preprocess_output='preprocess.output',
17581745
preprocess_include=None,
@@ -1779,6 +1766,16 @@ def parse(self, preprocess_output='preprocess.output', debug=0):
17791766
def get_directives(self):
17801767
return self.directives
17811768

1769+
#-------------------------------------------------------------------------------
1770+
def parse(filelist, preprocess_include=None, preprocess_define=None):
1771+
codeparser = VerilogCodeParser(filelist,
1772+
preprocess_include=preprocess_include,
1773+
preprocess_define=preprocess_define)
1774+
ast = codeparser.parse()
1775+
directives = codeparser.get_directives()
1776+
return ast, directives
1777+
1778+
#-------------------------------------------------------------------------------
17821779
if __name__ == '__main__':
17831780
from optparse import OptionParser
17841781

@@ -1811,12 +1808,10 @@ def showVersion():
18111808
if len(filelist) == 0:
18121809
showVersion()
18131810

1814-
codeparser = VerilogCodeParser(filelist,
1815-
preprocess_include=options.include,
1816-
preprocess_define=options.define)
1817-
ast = codeparser.parse()
1818-
directives = codeparser.get_directives()
1819-
1811+
ast, directives = parse(filelist,
1812+
preprocess_include=options.include,
1813+
preprocess_define=options.define)
1814+
18201815
ast.show()
18211816
for lineno, directive in directives:
18221817
print('Line %d : %s' % (lineno, directive))

‎pyverilog/vparser/preprocessor.py‎

Lines changed: 50 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
#-------------------------------------------------------------------------------
22
# preprocessor.py
33
#
4-
# Preprocessor
5-
#
6-
# Current version calls Icarus Verilog as preprocessor.
4+
# Verilog Preprocessor
5+
#
6+
# Icarus Verilog is used as a preprocessor via command-line.
77
# Please install Icarus Verilog on your environment.
88
#
99
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
@@ -15,6 +15,8 @@
1515
import subprocess
1616
import re
1717

18+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
19+
1820
class VerilogPreprocessor(object):
1921
def __init__(self, filelist, outputfile='pp.out', include=None, define=None):
2022
self.filelist = filelist
@@ -39,10 +41,49 @@ def preprocess(self):
3941
cmd += ' ' + f
4042
subprocess.call(cmd, shell=True)
4143

44+
#-------------------------------------------------------------------------------
45+
def preprocess(filelist,
46+
output='preprocess.output', include=None, define=None):
47+
pre = VerilogPreprocessor(filelist, output, include, define)
48+
pre.preprocess()
49+
text = open(output).read()
50+
os.remove(output)
51+
return text
52+
53+
#-------------------------------------------------------------------------------
4254
if __name__ == '__main__':
43-
filelist = ('../testcode/test.v',)
44-
pp_outputfile = 'pp.out'
45-
vp = VerilogPreprocessor(filelist, pp_outputfile, include=('./'))
46-
vp.preprocess()
47-
rslt = open(pp_outputfile, 'r').read()
48-
print(rslt)
55+
import pyverilog.utils.version
56+
from optparse import OptionParser
57+
58+
INFO = "Verilog Preprocessor"
59+
VERSION = pyverilog.utils.version.VERSION
60+
USAGE = "Usage: python preprocessor.py file ..."
61+
62+
def showVersion():
63+
print(INFO)
64+
print(VERSION)
65+
print(USAGE)
66+
sys.exit()
67+
68+
optparser = OptionParser()
69+
optparser.add_option("-v","--version",action="store_true",dest="showversion",
70+
default=False,help="Show the version")
71+
optparser.add_option("-I","--include",dest="include",action="append",
72+
default=[],help="Include path")
73+
optparser.add_option("-D",dest="define",action="append",
74+
default=[],help="Macro Definition")
75+
(options, args) = optparser.parse_args()
76+
77+
filelist = args
78+
if options.showversion:
79+
showVersion()
80+
81+
for f in filelist:
82+
if not os.path.exists(f): raise IOError("file not found: " + f)
83+
84+
if len(filelist) == 0:
85+
showVersion()
86+
87+
text = preprocess(filelist, include=options.include, define=options.define)
88+
89+
print(text)

‎test/Makefile‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
.PHONY: all
2+
all: clean
3+
4+
.PHONY: test
5+
test:
6+
find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {}
7+
8+
.PHONY: clean
9+
clean:
10+
find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {}

‎test/parser_test/Makefile‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
TEST=test.py
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: test
14+
test:
15+
$(PYTHON) -m pytest -vv $(TEST)
16+
17+
.PHONY: clean
18+
clean:
19+
rm -rf *.pyc __pycache__ parsetab.py *.out

‎test/parser_test/led.v‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
module led #
2+
(
3+
parameter STEP = 10
4+
)
5+
(
6+
input CLK,
7+
input RST,
8+
output reg [7:0] LED
9+
);
10+
11+
reg [31:0] count;
12+
13+
always @(posedge CLK) begin
14+
if(RST) begin
15+
count <= 0;
16+
LED <= 0;
17+
end else begin
18+
if(count == STEP - 1) begin
19+
count <= 0;
20+
LED <= LED + 1;
21+
end else begin
22+
count <= count + 1;
23+
end
24+
end
25+
end
26+
endmodule

‎test/parser_test/main.v‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
`default_nettype none
2+
`include "led.v"
3+
4+
module main
5+
(
6+
input CLK,
7+
input RST,
8+
output [7:0] LED
9+
);
10+
11+
led #
12+
(
13+
.STEP(`STEP)
14+
)
15+
inst_led
16+
(
17+
.CLK(CLK),
18+
.RST(RST),
19+
.LED(LED)
20+
);
21+
22+
endmodule

‎test/parser_test/pyverilog‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../../pyverilog

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