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arm64: errata: Expand speculative SSBS workaround (again)
JIRA: https://issues.redhat.com/browse/RHEL-108306 Note: There is a touch of fuzz here because the order of the v1/v2/v3 is wrong wrt upstream. commit adeec61 Author: Mark Rutland <mark.rutland@arm.com> Date: Thu Aug 1 11:18:03 2024 +0100 arm64: errata: Expand speculative SSBS workaround (again) A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We worked around this for a number of CPUs in commits: * 7187bb7 ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") * 75b3c43 ("arm64: errata: Expand speculative SSBS workaround") Since then, similar errata have been published for a number of other Arm Ltd CPUs, for which the same mitigation is sufficient. This is described in their respective Software Developer Errata Notice (SDEN) documents: * Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 https://developer.arm.com/documentation/SDEN-885749/3100/ * Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 https://developer.arm.com/documentation/SDEN-1152370/1900/ * Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 https://developer.arm.com/documentation/SDEN-1401784/2100/ * Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 https://developer.arm.com/documentation/SDEN-1707916/1600/ * Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 https://developer.arm.com/documentation/SDEN-2004089/1000/ * Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 https://developer.arm.com/documentation/SDEN-2832921/0500/ * Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 https://developer.arm.com/documentation/SDEN-1401782/2100/ * Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 https://developer.arm.com/documentation/SDEN-1707914/1600/ * Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 https://developer.arm.com/documentation/SDEN-885747/3200/ * Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 https://developer.arm.com/documentation/SDEN-1401781/1900/ Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number and some CPUs have multiple erratum numbers for the same HW issue. On parts without SB, it is necessary to use ISB for the workaround. The spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" sequence in this case, which is sufficient on all affected parts. Enable the existing mitigation by adding the relevant MIDRs to erratum_spec_ssbs_list. The list is sorted alphanumerically (involving moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and potentially extend again in future. The Kconfig text is also updated to clarify the set of affected parts and the mitigation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jeremy Linton <jlinton@redhat.com>
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‎Documentation/arm64/silicon-errata.rst‎

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@@ -126,17 +126,27 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1490853 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1491015 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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<<<<<<< HEAD:Documentation/arm64/silicon-errata.rst
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
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=======
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| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
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>>>>>>> adeec61a4723 (arm64: errata: Expand speculative SSBS workaround (again)):Documentation/arch/arm64/silicon-errata.rst
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
@@ -150,8 +160,14 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #1502854 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #1619801 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #1619801 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA|
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| | | #562869,1047329 | |
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+----------------+-----------------+-----------------+-----------------------------+

‎arch/arm64/Kconfig‎

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@@ -1058,30 +1058,40 @@ config ARM64_ERRATUM_3117295
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If unsure, say Y.
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config ARM64_ERRATUM_3194386
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bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
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bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
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default y
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help
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This option adds the workaround for the following errata:
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* ARM Cortex-A76 erratum 3324349
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* ARM Cortex-A77 erratum 3324348
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* ARM Cortex-A78 erratum 3324344
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* ARM Cortex-A78C erratum 3324346
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* ARM Cortex-A78C erratum 3324347
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* ARM Cortex-A710 erratam 3324338
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* ARM Cortex-A720 erratum 3456091
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* ARM Cortex-A725 erratum 3456106
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* ARM Cortex-X1 erratum 3324344
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* ARM Cortex-X1C erratum 3324346
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* ARM Cortex-X2 erratum 3324338
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* ARM Cortex-X3 erratum 3324335
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* ARM Cortex-X4 erratum 3194386
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* ARM Cortex-X925 erratum 3324334
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* ARM Neoverse-N1 erratum 3324349
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* ARM Neoverse N2 erratum 3324339
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* ARM Neoverse-V1 erratum 3324341
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* ARM Neoverse V2 erratum 3324336
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* ARM Neoverse-V3 erratum 3312417
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On affected cores "MSR SSBS, #0" instructions may not affect
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subsequent speculative instructions, which may permit unexepected
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speculative store bypassing.
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Work around this problem by placing a speculation barrier after
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kernel changes to SSBS. The presence of the SSBS special-purpose
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register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
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that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
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SSBS.
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Work around this problem by placing a Speculation Barrier (SB) or
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Instruction Synchronization Barrier (ISB) after kernel changes to
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SSBS. The presence of the SSBS special-purpose register is hidden
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from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
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will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
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If unsure, say Y.
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‎arch/arm64/kernel/cpu_errata.c‎

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@@ -434,15 +434,24 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_3194386
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static const struct midr_range erratum_spec_ssbs_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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{}
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};
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#endif

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