drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation

jira NONE_AUTOMATION
Rebuild_History Non-Buildable kernel-5.14.0-570.18.1.el9_6
commit-author Imre Deak <imre.deak@intel.com>
commit 802a69b
Empty-Commit: Cherry-Pick Conflicts during history rebuild.
Will be included in final tarball splat. Ref for failed cherry-pick at:
ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/802a69b6.failed

The MST branch device may not support the number of DSC slices a mode
requires, handle the error in this case.

Fixes: 4e0837a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation")
	Cc: stable@vger.kernel.org # v6.8+
	Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
	Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-1-imre.deak@intel.com
(cherry picked from commit 802a69b)
	Signed-off-by: Jonathan Maple <jmaple@ciq.com>

# Conflicts:
#	drivers/gpu/drm/i915/display/intel_dp_mst.c

Author: PlaidCat

ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/802a69b6.failed

@@ -0,0 +1,40 @@
+drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation
+
+jira NONE_AUTOMATION
+Rebuild_History Non-Buildable kernel-5.14.0-570.18.1.el9_6
+commit-author Imre Deak <imre.deak@intel.com>
+commit 802a69b6b8a0502a9e2309afec7e1b77f67874f2
+Empty-Commit: Cherry-Pick Conflicts during history rebuild.
+Will be included in final tarball splat. Ref for failed cherry-pick at:
+ciq/ciq_backports/kernel-5.14.0-570.18.1.el9_6/802a69b6.failed
+
+The MST branch device may not support the number of DSC slices a mode
+requires, handle the error in this case.
+
+Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation")
+	Cc: stable@vger.kernel.org # v6.8+
+	Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+	Signed-off-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-1-imre.deak@intel.com
+(cherry picked from commit 802a69b6b8a0502a9e2309afec7e1b77f67874f2)
+	Signed-off-by: Jonathan Maple <jmaple@ciq.com>
+
+# Conflicts:
+#	drivers/gpu/drm/i915/display/intel_dp_mst.c
+diff --cc drivers/gpu/drm/i915/display/intel_dp_mst.c
+index 3dc3c85fef64,2822ae116003..000000000000
+--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
+@@@ -152,7 -153,7 +152,11 @@@ static int intel_dp_mst_dsc_get_slice_c
+  {
+  	const struct drm_display_mode *adjusted_mode =
+  		&crtc_state->hw.adjusted_mode;
+++<<<<<<< HEAD
+ +	int num_joined_pipes = crtc_state->joiner_pipes;
+++=======
++ 	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
+++>>>>>>> 802a69b6b8a0 (drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation)
+  
+  	return intel_dp_dsc_get_slice_count(connector,
+  					    adjusted_mode->clock,
+* Unmerged path drivers/gpu/drm/i915/display/intel_dp_mst.c