@@ -80,7 +80,7 @@ static inline u32 shadow_sr_wr_ind_addr(struct ath10k *ar,
8080
8181static inline unsigned int
8282ath10k_set_ring_byte (unsigned int offset ,
83- struct ath10k_hw_ce_regs_addr_map * addr_map )
83+ const struct ath10k_hw_ce_regs_addr_map * addr_map )
8484{
8585 return ((offset << addr_map -> lsb ) & addr_map -> mask );
8686}
@@ -203,7 +203,7 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
203203 u32 ce_ctrl_addr ,
204204 unsigned int n )
205205{
206- struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
206+ const struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
207207
208208 u32 ctrl1_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
209209 ctrl_regs -> addr );
@@ -217,7 +217,7 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
217217 u32 ce_ctrl_addr ,
218218 unsigned int n )
219219{
220- struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
220+ const struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
221221
222222 u32 ctrl1_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
223223 ctrl_regs -> addr );
@@ -231,7 +231,7 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
231231 u32 ce_ctrl_addr ,
232232 unsigned int n )
233233{
234- struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
234+ const struct ath10k_hw_ce_ctrl1 * ctrl_regs = ar -> hw_ce_regs -> ctrl1_regs ;
235235
236236 u32 ctrl1_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
237237 ctrl_regs -> addr );
@@ -313,7 +313,7 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
313313 u32 ce_ctrl_addr ,
314314 unsigned int n )
315315{
316- struct ath10k_hw_ce_dst_src_wm_regs * srcr_wm = ar -> hw_ce_regs -> wm_srcr ;
316+ const struct ath10k_hw_ce_dst_src_wm_regs * srcr_wm = ar -> hw_ce_regs -> wm_srcr ;
317317 u32 addr = ath10k_ce_read32 (ar , ce_ctrl_addr + srcr_wm -> addr );
318318
319319 ath10k_ce_write32 (ar , ce_ctrl_addr + srcr_wm -> addr ,
@@ -325,7 +325,7 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
325325 u32 ce_ctrl_addr ,
326326 unsigned int n )
327327{
328- struct ath10k_hw_ce_dst_src_wm_regs * srcr_wm = ar -> hw_ce_regs -> wm_srcr ;
328+ const struct ath10k_hw_ce_dst_src_wm_regs * srcr_wm = ar -> hw_ce_regs -> wm_srcr ;
329329 u32 addr = ath10k_ce_read32 (ar , ce_ctrl_addr + srcr_wm -> addr );
330330
331331 ath10k_ce_write32 (ar , ce_ctrl_addr + srcr_wm -> addr ,
@@ -337,7 +337,7 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
337337 u32 ce_ctrl_addr ,
338338 unsigned int n )
339339{
340- struct ath10k_hw_ce_dst_src_wm_regs * dstr_wm = ar -> hw_ce_regs -> wm_dstr ;
340+ const struct ath10k_hw_ce_dst_src_wm_regs * dstr_wm = ar -> hw_ce_regs -> wm_dstr ;
341341 u32 addr = ath10k_ce_read32 (ar , ce_ctrl_addr + dstr_wm -> addr );
342342
343343 ath10k_ce_write32 (ar , ce_ctrl_addr + dstr_wm -> addr ,
@@ -349,7 +349,7 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
349349 u32 ce_ctrl_addr ,
350350 unsigned int n )
351351{
352- struct ath10k_hw_ce_dst_src_wm_regs * dstr_wm = ar -> hw_ce_regs -> wm_dstr ;
352+ const struct ath10k_hw_ce_dst_src_wm_regs * dstr_wm = ar -> hw_ce_regs -> wm_dstr ;
353353 u32 addr = ath10k_ce_read32 (ar , ce_ctrl_addr + dstr_wm -> addr );
354354
355355 ath10k_ce_write32 (ar , ce_ctrl_addr + dstr_wm -> addr ,
@@ -360,7 +360,7 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
360360static inline void ath10k_ce_copy_complete_inter_enable (struct ath10k * ar ,
361361 u32 ce_ctrl_addr )
362362{
363- struct ath10k_hw_ce_host_ie * host_ie = ar -> hw_ce_regs -> host_ie ;
363+ const struct ath10k_hw_ce_host_ie * host_ie = ar -> hw_ce_regs -> host_ie ;
364364
365365 u32 host_ie_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
366366 ar -> hw_ce_regs -> host_ie_addr );
@@ -372,7 +372,7 @@ static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
372372static inline void ath10k_ce_copy_complete_intr_disable (struct ath10k * ar ,
373373 u32 ce_ctrl_addr )
374374{
375- struct ath10k_hw_ce_host_ie * host_ie = ar -> hw_ce_regs -> host_ie ;
375+ const struct ath10k_hw_ce_host_ie * host_ie = ar -> hw_ce_regs -> host_ie ;
376376
377377 u32 host_ie_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
378378 ar -> hw_ce_regs -> host_ie_addr );
@@ -384,7 +384,7 @@ static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
384384static inline void ath10k_ce_watermark_intr_disable (struct ath10k * ar ,
385385 u32 ce_ctrl_addr )
386386{
387- struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
387+ const struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
388388
389389 u32 host_ie_addr = ath10k_ce_read32 (ar , ce_ctrl_addr +
390390 ar -> hw_ce_regs -> host_ie_addr );
@@ -396,7 +396,7 @@ static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
396396static inline void ath10k_ce_error_intr_disable (struct ath10k * ar ,
397397 u32 ce_ctrl_addr )
398398{
399- struct ath10k_hw_ce_misc_regs * misc_regs = ar -> hw_ce_regs -> misc_regs ;
399+ const struct ath10k_hw_ce_misc_regs * misc_regs = ar -> hw_ce_regs -> misc_regs ;
400400
401401 u32 misc_ie_addr = ath10k_ce_read32 (ar ,
402402 ce_ctrl_addr + ar -> hw_ce_regs -> misc_ie_addr );
@@ -410,7 +410,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
410410 u32 ce_ctrl_addr ,
411411 unsigned int mask )
412412{
413- struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
413+ const struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
414414
415415 ath10k_ce_write32 (ar , ce_ctrl_addr + wm_regs -> addr , mask );
416416}
@@ -1230,7 +1230,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
12301230{
12311231 struct ath10k_ce * ce = ath10k_ce_priv (ar );
12321232 struct ath10k_ce_pipe * ce_state = & ce -> ce_states [ce_id ];
1233- struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
1233+ const struct ath10k_hw_ce_host_wm_regs * wm_regs = ar -> hw_ce_regs -> wm_regs ;
12341234 u32 ctrl_addr = ce_state -> ctrl_addr ;
12351235
12361236 /*
@@ -1388,7 +1388,7 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
13881388 ath10k_ce_src_ring_highmark_set (ar , ctrl_addr , nentries );
13891389
13901390 ath10k_dbg (ar , ATH10K_DBG_BOOT ,
1391- "boot init ce src ring id %d entries %d base_addr %pK \n" ,
1391+ "boot init ce src ring id %d entries %d base_addr %p \n" ,
13921392 ce_id , nentries , src_ring -> base_addr_owner_space );
13931393
13941394 return 0 ;
@@ -1426,7 +1426,7 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
14261426 ath10k_ce_dest_ring_highmark_set (ar , ctrl_addr , nentries );
14271427
14281428 ath10k_dbg (ar , ATH10K_DBG_BOOT ,
1429- "boot ce dest ring id %d entries %d base_addr %pK \n" ,
1429+ "boot ce dest ring id %d entries %d base_addr %p \n" ,
14301430 ce_id , nentries , dest_ring -> base_addr_owner_space );
14311431
14321432 return 0 ;
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