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Merge: Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/1502 JIRA: https://issues.redhat.com/browse/RHEL-116889 ARK-MR: cki-project/kernel-ark!4222 The SoC series S32G2xx and S32G3xx feature one DWMAC instance, the SoC S32R45 has two instances. The series adds the support for it. Signed-off-by: Alessandro Carminati <acarmina@redhat.com> Approved-by: Michal Schmidt <mschmidt@redhat.com> Approved-by: Jared Kangas <jkangas@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
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‎Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2021-2024 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
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maintainers:
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- Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
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description:
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This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
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The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
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the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
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interface over Pinctrl device or the output can be routed
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to the embedded SerDes for SGMII connectivity.
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properties:
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compatible:
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oneOf:
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- const: nxp,s32g2-dwmac
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- items:
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- enum:
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- nxp,s32g3-dwmac
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- nxp,s32r45-dwmac
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- const: nxp,s32g2-dwmac
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reg:
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items:
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- description: Main GMAC registers
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- description: GMAC PHY mode control register
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interrupts:
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maxItems: 1
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interrupt-names:
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const: macirq
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clocks:
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items:
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- description: Main GMAC clock
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- description: Transmit clock
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- description: Receive clock
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- description: PTP reference clock
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clock-names:
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items:
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- const: stmmaceth
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- const: tx
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- const: rx
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- const: ptp_ref
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required:
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- clocks
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- clock-names
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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ethernet@4033c000 {
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compatible = "nxp,s32g2-dwmac";
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reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
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<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
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clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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};

‎Documentation/devicetree/bindings/net/snps,dwmac.yaml‎

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- ingenic,x2000-mac
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- loongson,ls2k-dwmac
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- loongson,ls7a-dwmac
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- nxp,s32g2-dwmac
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- qcom,qcs404-ethqos
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- qcom,sa8775p-ethqos
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- qcom,sc8280xp-ethqos

‎MAINTAINERS‎

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@@ -2832,6 +2832,13 @@ F: arch/arm64/boot/dts/freescale/s32g*.dts*
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F: drivers/pinctrl/nxp/
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F: drivers/rtc/rtc-s32g.c
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ARM/NXP S32G/S32R DWMAC ETHERNET DRIVER
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M: Jan Petrous <jan.petrous@oss.nxp.com>
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L: NXP S32 Linux Team <s32@nxp.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
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F: drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
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ARM/Orion SoC/Technologic Systems TS-78xx platform support
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M: Alexander Clouter <alex@digriz.org.uk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

‎drivers/net/ethernet/apm/xgene/xgene_enet_hw.c‎

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@@ -421,18 +421,12 @@ static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
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422422
if (dev->of_node) {
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struct clk *parent = clk_get_parent(pdata->clk);
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long rate = rgmii_clock(pdata->phy_speed);
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switch (pdata->phy_speed) {
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case SPEED_10:
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clk_set_rate(parent, 2500000);
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break;
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case SPEED_100:
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clk_set_rate(parent, 25000000);
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break;
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default:
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clk_set_rate(parent, 125000000);
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break;
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}
426+
if (rate < 0)
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rate = 125000000;
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clk_set_rate(parent, rate);
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}
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#ifdef CONFIG_ACPI
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else {

‎drivers/net/ethernet/cadence/macb_main.c‎

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@@ -530,19 +530,9 @@ static void macb_set_tx_clk(struct macb *bp, int speed)
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if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
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return;
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533-
switch (speed) {
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case SPEED_10:
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rate = 2500000;
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break;
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case SPEED_100:
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rate = 25000000;
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break;
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case SPEED_1000:
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rate = 125000000;
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break;
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default:
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rate = rgmii_clock(speed);
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if (rate < 0)
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return;
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}
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rate_rounded = clk_round_rate(bp->tx_clk, rate);
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if (rate_rounded < 0)

‎drivers/net/ethernet/stmicro/stmmac/Kconfig‎

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the stmmac device driver. This support can make use of a custom MII
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converter PCS device.
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config DWMAC_S32
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tristate "NXP S32G/S32R GMAC support"
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default ARCH_S32
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depends on OF && (ARCH_S32 || COMPILE_TEST)
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help
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Support for ethernet controller on NXP S32CC SOCs.
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This selects NXP SoC glue layer support for the stmmac
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device driver. This driver is used for the S32CC series
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SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
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S32R45.
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config DWMAC_SOCFPGA
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tristate "SOCFPGA dwmac support"
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default ARCH_INTEL_SOCFPGA

‎drivers/net/ethernet/stmicro/stmmac/Makefile‎

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@@ -22,6 +22,7 @@ obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
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obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
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obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o
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obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
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obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o
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obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o

‎drivers/net/ethernet/stmicro/stmmac/common.h‎

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#define CSR_F_150M 150000000
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#define CSR_F_250M 250000000
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#define CSR_F_300M 300000000
260+
#define CSR_F_500M 500000000
261+
#define CSR_F_800M 800000000
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#define MAC_CSR_H_FRQ_MASK 0x20
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‎drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c‎

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@@ -186,7 +186,7 @@ static void imx_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mod
186186
{
187187
struct plat_stmmacenet_data *plat_dat;
188188
struct imx_priv_data *dwmac = priv;
189-
unsigned long rate;
189+
long rate;
190190
int err;
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192192
plat_dat = dwmac->plat_dat;
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196196
(plat_dat->mac_interface == PHY_INTERFACE_MODE_MII))
197197
return;
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199-
switch (speed) {
200-
case SPEED_1000:
201-
rate = 125000000;
202-
break;
203-
case SPEED_100:
204-
rate = 25000000;
205-
break;
206-
case SPEED_10:
207-
rate = 2500000;
208-
break;
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default:
199+
rate = rgmii_clock(speed);
200+
if (rate < 0) {
210201
dev_err(dwmac->dev, "invalid speed %u\n", speed);
211202
return;
212203
}

‎drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c‎

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@@ -31,27 +31,13 @@ struct intel_dwmac_data {
3131
static void kmb_eth_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
3232
{
3333
struct intel_dwmac *dwmac = priv;
34-
unsigned long rate;
34+
long rate;
3535
int ret;
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37-
rate = clk_get_rate(dwmac->tx_clk);
38-
39-
switch (speed) {
40-
case SPEED_1000:
41-
rate = 125000000;
42-
break;
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44-
case SPEED_100:
45-
rate = 25000000;
46-
break;
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48-
case SPEED_10:
49-
rate = 2500000;
50-
break;
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52-
default:
37+
rate = rgmii_clock(speed);
38+
if (rate < 0) {
5339
dev_err(dwmac->dev, "Invalid speed\n");
54-
break;
40+
return;
5541
}
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5743
ret = clk_set_rate(dwmac->tx_clk, rate);

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