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AzharMCHPcfriedt
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dts: arm: microchip: add dtsi files for Microchip PIC32CZ CA SoC series
Adds common and SoC-specific .dtsi files for the Microchip PIC32CZ CA80 CA90 and CA91 family. These files define core peripherals, address maps, and interrupt controller structure shared across the PIC32CZ CA80 9x variants. Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
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‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_1051_ca.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(1)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(512)>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_2051_ca.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(2)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(512)>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_4010_ca.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(4)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_M(1)>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_8110_ca.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(8)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_M(1)>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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write-block-size = <8>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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porta: gpio@44840000 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840000 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portb: gpio@44840080 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840080 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portc: gpio@44840100 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840100 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portd: gpio@44840180 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840180 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_100.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_144.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_176.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>
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/ {
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soc {
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porte: gpio@44840200 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840200 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portf: gpio@44840280 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840280 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portg: gpio@44840300 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840300 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_208.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>
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/ {
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soc {
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porte: gpio@44840200 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840200 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portf: gpio@44840280 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840280 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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portg: gpio@44840300 {
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status = "disabled";
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compatible = "microchip,port-g1-gpio";
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reg = <0x44840300 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#microchip,pin-cells = <2>;
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};
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};
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};

‎dts/arm/microchip/pic32c/pic32cz_ca/pic32cz_ca80/pic32cz2051ca80100.dtsi‎

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca_100.dtsi>
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#include <microchip/pic32c/pic32cz_ca/common/pic32cz_2051_ca.dtsi>

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