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[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)
The Xqcili extension includes a two instructions that load large immediates than is available with the base RISC-V ISA. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -202,6 +202,7 @@
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
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// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension)
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// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)

‎llvm/docs/RISCVUsage.rst‎

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@@ -456,6 +456,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcili``
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LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilia``
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LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
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Changes to the RISC-V Backend
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-----------------------------
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* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large Immediate)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit Manipulation)

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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VK == RISCVMCExpr::VK_RISCV_None;
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}
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bool isSImm20() const {
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if (!isImm())
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return false;
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RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
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int64_t Imm;
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bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
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return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
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isInt<20>(fixImmediateForRV32(Imm, isRV64Imm()));
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}
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bool isSImm26() const {
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if (!isImm())
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return false;
@@ -1712,6 +1722,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidSImm26:
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return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
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(1 << 25) - 1);
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case Match_InvalidSImm20:
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return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 19),
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(1 << 19) - 1);
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case Match_InvalidSImm32:
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return generateImmOutOfRangeError(Operands, ErrorInfo,
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std::numeric_limits<int32_t>::min(),

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -651,8 +651,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
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RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli,
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RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics,
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RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
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RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
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RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
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RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
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RISCV::FeatureVendorXqcisls,
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};
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static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -329,6 +329,7 @@ enum OperandType : unsigned {
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OPERAND_SIMM11,
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OPERAND_SIMM12,
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OPERAND_SIMM12_LSB00000,
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OPERAND_SIMM20,
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OPERAND_SIMM26,
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OPERAND_SIMM32,
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OPERAND_CLUI_IMM,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1359,6 +1359,14 @@ def HasVendorXqciint
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AssemblerPredicate<(all_of FeatureVendorXqciint),
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"'Xqciint' (Qualcomm uC Interrupts Extension)">;
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def FeatureVendorXqcili
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
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[FeatureStdExtZca]>;
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def HasVendorXqcili : Predicate<"Subtarget->hasVendorXqcili()">,
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AssemblerPredicate<(all_of FeatureVendorXqcili),
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"'Xqcili' (Qualcomm uC Load Large Immediate Extension)">;
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def FeatureVendorXqcilia
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
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[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -56,6 +56,8 @@ def uimm11 : RISCVUImmLeafOp<11>;
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def simm11 : RISCVSImmLeafOp<11>;
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def simm20 : RISCVSImmLeafOp<20>;
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def simm26 : RISCVSImmLeafOp<26>;
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// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
@@ -591,6 +593,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
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def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
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} // Predicates = [HasVendorXqcilo, IsRV32]
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let Predicates = [HasVendorXqcili, IsRV32] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_LI : RVInstU<OPC_OP_IMM_32, (outs GPRNoX0:$rd), (ins simm20:$imm20),
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"qc.li", "$rd, $imm20"> {
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let Inst{31} = imm20{19};
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let Inst{30-16} = imm20{14-0};
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let Inst{15-12} = imm20{18-15};
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}
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def QC_E_LI : QCIRVInstEAI<0b000, 0b0, "qc.e.li">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcili, IsRV32]
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let Predicates = [HasVendorXqcilia, IsRV32] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -744,9 +744,9 @@ Error RISCVISAInfo::checkDependency() {
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bool HasXqccmp = Exts.count("xqccmp") != 0;
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"},
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{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"},
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{"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"}, {"xqcicm"},
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{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcili"}, {"xqcilia"},
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{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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static constexpr StringLiteral ZcdOverlaps[] = {
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{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
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‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -90,6 +90,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
@@ -412,6 +413,7 @@
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; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
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; RV32XQCILI: .attribute 5, "rv32i2p1_zca1p0_xqcili0p2"
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; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
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; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
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; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"

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