codal_port/ticks_cpu: Check CoreDebug DEMCR trace enable bit.

microbit-carlos · microbit-carlos · commit 90b9b7d3dd30 · 2024-04-16T14:36:45.000+01:00
The DAPLink controlled reset button performs a target reset via SWD, and the CoreDebug trace enable bit seems to be cleared while the DWT->CTRL cycle count enable bit is not. #179 (comment)
diff --git a/src/codal_port/mphalport.h b/src/codal_port/mphalport.h
@@ -46,7 +46,7 @@ static inline void enable_irq(uint32_t state) {
 }
 
 static inline mp_uint_t mp_hal_ticks_cpu(void) {
-    if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {
+    if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) || !(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)) {
         CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
         DWT->CYCCNT = 0;
         DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;

Original file line number	Diff line number	Diff line change
`@@ -46,7 +46,7 @@ static inline void enable_irq(uint32_t state) {`
`46`	`46`	`}`
`47`	`47`
`48`	`48`	`static inline mp_uint_t mp_hal_ticks_cpu(void) {`
`49`		`- if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {`
	`49`	`+ if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) \|\| !(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)) {`
`50`	`50`	`CoreDebug->DEMCR \|= CoreDebug_DEMCR_TRCENA_Msk;`
`51`	`51`	`DWT->CYCCNT = 0;`
`52`	`52`	`DWT->CTRL \|= DWT_CTRL_CYCCNTENA_Msk;`