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Herton R. Krzesinski
committed
Merge: arm-smmu-qcom: update to 6.2-rc5
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/1952 Bugzilla: https://bugzilla.redhat.com/2164639 Update arm-smmu-qcom to 6.2-rc5 Signed-off-by: Adrien Thierry <athierry@redhat.com> Approved-by: Mark Langsdorf <mlangsdo@redhat.com> Approved-by: Donald Dutile <ddutile@redhat.com> Approved-by: Eric Chanudet <echanude@redhat.com> Approved-by: Brian Masney <bmasney@redhat.com> Approved-by: Jerry Snitselaar <jsnitsel@redhat.com> Approved-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Herton R. Krzesinski <herton@redhat.com>
2 parents 3f183a8 + 740f85f commit c9afa88

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3 files changed

+130
-139
lines changed

3 files changed

+130
-139
lines changed

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c‎

Lines changed: 0 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -10,16 +10,6 @@
1010
#include "arm-smmu.h"
1111
#include "arm-smmu-qcom.h"
1212

13-
enum qcom_smmu_impl_reg_offset {
14-
QCOM_SMMU_TBU_PWR_STATUS,
15-
QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
16-
QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
17-
};
18-
19-
struct qcom_smmu_config {
20-
const u32 *reg_offset;
21-
};
22-
2313
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
2414
{
2515
int ret;
@@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
5949
tbu_pwr_status, sync_inv_ack, sync_inv_progress);
6050
}
6151
}
62-
63-
/* Implementation Defined Register Space 0 register offsets */
64-
static const u32 qcom_smmu_impl0_reg_offset[] = {
65-
[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
66-
[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
67-
[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
68-
};
69-
70-
static const struct qcom_smmu_config qcm2290_smmu_cfg = {
71-
.reg_offset = qcom_smmu_impl0_reg_offset,
72-
};
73-
74-
static const struct qcom_smmu_config sc7180_smmu_cfg = {
75-
.reg_offset = qcom_smmu_impl0_reg_offset,
76-
};
77-
78-
static const struct qcom_smmu_config sc7280_smmu_cfg = {
79-
.reg_offset = qcom_smmu_impl0_reg_offset,
80-
};
81-
82-
static const struct qcom_smmu_config sc8180x_smmu_cfg = {
83-
.reg_offset = qcom_smmu_impl0_reg_offset,
84-
};
85-
86-
static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
87-
.reg_offset = qcom_smmu_impl0_reg_offset,
88-
};
89-
90-
static const struct qcom_smmu_config sm6125_smmu_cfg = {
91-
.reg_offset = qcom_smmu_impl0_reg_offset,
92-
};
93-
94-
static const struct qcom_smmu_config sm6350_smmu_cfg = {
95-
.reg_offset = qcom_smmu_impl0_reg_offset,
96-
};
97-
98-
static const struct qcom_smmu_config sm8150_smmu_cfg = {
99-
.reg_offset = qcom_smmu_impl0_reg_offset,
100-
};
101-
102-
static const struct qcom_smmu_config sm8250_smmu_cfg = {
103-
.reg_offset = qcom_smmu_impl0_reg_offset,
104-
};
105-
106-
static const struct qcom_smmu_config sm8350_smmu_cfg = {
107-
.reg_offset = qcom_smmu_impl0_reg_offset,
108-
};
109-
110-
static const struct qcom_smmu_config sm8450_smmu_cfg = {
111-
.reg_offset = qcom_smmu_impl0_reg_offset,
112-
};
113-
114-
static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
115-
{ .compatible = "qcom,msm8998-smmu-v2" },
116-
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
117-
{ .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
118-
{ .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
119-
{ .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
120-
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
121-
{ .compatible = "qcom,sdm630-smmu-v2" },
122-
{ .compatible = "qcom,sdm845-smmu-500" },
123-
{ .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
124-
{ .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
125-
{ .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
126-
{ .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
127-
{ .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
128-
{ .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
129-
{ }
130-
};
131-
132-
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
133-
{
134-
const struct of_device_id *match;
135-
const struct device_node *np = smmu->dev->of_node;
136-
137-
match = of_match_node(qcom_smmu_impl_debug_match, np);
138-
if (!match)
139-
return NULL;
140-
141-
return match->data;
142-
}

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c‎

Lines changed: 114 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
361361
{
362362
int ret;
363363

364+
arm_mmu500_reset(smmu);
365+
364366
/*
365367
* To address performance degradation in non-real time clients,
366368
* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
@@ -374,41 +376,67 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
374376
return ret;
375377
}
376378

377-
static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
378-
{
379-
const struct device_node *np = smmu->dev->of_node;
380-
381-
arm_mmu500_reset(smmu);
382-
383-
if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
384-
return qcom_sdm845_smmu500_reset(smmu);
379+
static const struct arm_smmu_impl qcom_smmu_v2_impl = {
380+
.init_context = qcom_smmu_init_context,
381+
.cfg_probe = qcom_smmu_cfg_probe,
382+
.def_domain_type = qcom_smmu_def_domain_type,
383+
.write_s2cr = qcom_smmu_write_s2cr,
384+
.tlb_sync = qcom_smmu_tlb_sync,
385+
};
385386

386-
return 0;
387-
}
387+
static const struct arm_smmu_impl qcom_smmu_500_impl = {
388+
.init_context = qcom_smmu_init_context,
389+
.cfg_probe = qcom_smmu_cfg_probe,
390+
.def_domain_type = qcom_smmu_def_domain_type,
391+
.reset = arm_mmu500_reset,
392+
.write_s2cr = qcom_smmu_write_s2cr,
393+
.tlb_sync = qcom_smmu_tlb_sync,
394+
};
388395

389-
static const struct arm_smmu_impl qcom_smmu_impl = {
396+
static const struct arm_smmu_impl sdm845_smmu_500_impl = {
390397
.init_context = qcom_smmu_init_context,
391398
.cfg_probe = qcom_smmu_cfg_probe,
392399
.def_domain_type = qcom_smmu_def_domain_type,
393-
.reset = qcom_smmu500_reset,
400+
.reset = qcom_sdm845_smmu500_reset,
394401
.write_s2cr = qcom_smmu_write_s2cr,
395402
.tlb_sync = qcom_smmu_tlb_sync,
396403
};
397404

398-
static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
405+
static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
406+
.init_context = qcom_adreno_smmu_init_context,
407+
.def_domain_type = qcom_smmu_def_domain_type,
408+
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
409+
.write_sctlr = qcom_adreno_smmu_write_sctlr,
410+
.tlb_sync = qcom_smmu_tlb_sync,
411+
};
412+
413+
static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
399414
.init_context = qcom_adreno_smmu_init_context,
400415
.def_domain_type = qcom_smmu_def_domain_type,
401-
.reset = qcom_smmu500_reset,
416+
.reset = arm_mmu500_reset,
402417
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
403418
.write_sctlr = qcom_adreno_smmu_write_sctlr,
404419
.tlb_sync = qcom_smmu_tlb_sync,
405420
};
406421

407422
static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
408-
const struct arm_smmu_impl *impl)
423+
const struct qcom_smmu_match_data *data)
409424
{
425+
const struct device_node *np = smmu->dev->of_node;
426+
const struct arm_smmu_impl *impl;
410427
struct qcom_smmu *qsmmu;
411428

429+
if (!data)
430+
return ERR_PTR(-EINVAL);
431+
432+
if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
433+
impl = data->adreno_impl;
434+
else
435+
impl = data->impl;
436+
437+
if (!impl)
438+
return smmu;
439+
412440
/* Check to make sure qcom_scm has finished probing */
413441
if (!qcom_scm_is_available())
414442
return ERR_PTR(-EPROBE_DEFER);
@@ -418,27 +446,77 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
418446
return ERR_PTR(-ENOMEM);
419447

420448
qsmmu->smmu.impl = impl;
421-
qsmmu->cfg = qcom_smmu_impl_data(smmu);
449+
qsmmu->cfg = data->cfg;
422450

423451
return &qsmmu->smmu;
424452
}
425453

454+
/* Implementation Defined Register Space 0 register offsets */
455+
static const u32 qcom_smmu_impl0_reg_offset[] = {
456+
[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
457+
[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
458+
[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
459+
};
460+
461+
static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
462+
.reg_offset = qcom_smmu_impl0_reg_offset,
463+
};
464+
465+
/*
466+
* It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
467+
* there are not enough context banks.
468+
*/
469+
static const struct qcom_smmu_match_data msm8996_smmu_data = {
470+
.impl = NULL,
471+
.adreno_impl = &qcom_adreno_smmu_v2_impl,
472+
};
473+
474+
static const struct qcom_smmu_match_data qcom_smmu_v2_data = {
475+
.impl = &qcom_smmu_v2_impl,
476+
.adreno_impl = &qcom_adreno_smmu_v2_impl,
477+
};
478+
479+
static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
480+
.impl = &sdm845_smmu_500_impl,
481+
/*
482+
* No need for adreno impl here. On sdm845 the Adreno SMMU is handled
483+
* by the separate sdm845-smmu-v2 device.
484+
*/
485+
/* Also no debug configuration. */
486+
};
487+
488+
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
489+
.impl = &qcom_smmu_500_impl,
490+
.adreno_impl = &qcom_adreno_smmu_500_impl,
491+
.cfg = &qcom_smmu_impl0_cfg,
492+
};
493+
494+
/*
495+
* Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
496+
* special handling and can not be covered by the qcom,smmu-500 entry.
497+
*/
426498
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
427-
{ .compatible = "qcom,msm8998-smmu-v2" },
428-
{ .compatible = "qcom,qcm2290-smmu-500" },
429-
{ .compatible = "qcom,sc7180-smmu-500" },
430-
{ .compatible = "qcom,sc7280-smmu-500" },
431-
{ .compatible = "qcom,sc8180x-smmu-500" },
432-
{ .compatible = "qcom,sc8280xp-smmu-500" },
433-
{ .compatible = "qcom,sdm630-smmu-v2" },
434-
{ .compatible = "qcom,sdm845-smmu-500" },
435-
{ .compatible = "qcom,sm6125-smmu-500" },
436-
{ .compatible = "qcom,sm6350-smmu-500" },
437-
{ .compatible = "qcom,sm6375-smmu-500" },
438-
{ .compatible = "qcom,sm8150-smmu-500" },
439-
{ .compatible = "qcom,sm8250-smmu-500" },
440-
{ .compatible = "qcom,sm8350-smmu-500" },
441-
{ .compatible = "qcom,sm8450-smmu-500" },
499+
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
500+
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
501+
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
502+
{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
503+
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
504+
{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
505+
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
506+
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
507+
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
508+
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
509+
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
510+
{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
511+
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
512+
{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
513+
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
514+
{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
515+
{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
516+
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
517+
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
518+
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
519+
{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
442520
{ }
443521
};
444522

@@ -453,26 +531,19 @@ static struct acpi_platform_list qcom_acpi_platlist[] = {
453531
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
454532
{
455533
const struct device_node *np = smmu->dev->of_node;
534+
const struct of_device_id *match;
456535

457536
#ifdef CONFIG_ACPI
458537
if (np == NULL) {
459538
/* Match platform for ACPI boot */
460539
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
461-
return qcom_smmu_create(smmu, &qcom_smmu_impl);
540+
return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
462541
}
463542
#endif
464543

465-
/*
466-
* Do not change this order of implementation, i.e., first adreno
467-
* smmu impl and then apss smmu since we can have both implementing
468-
* arm,mmu-500 in which case we will miss setting adreno smmu specific
469-
* features if the order is changed.
470-
*/
471-
if (of_device_is_compatible(np, "qcom,adreno-smmu"))
472-
return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
473-
474-
if (of_match_node(qcom_smmu_impl_of_match, np))
475-
return qcom_smmu_create(smmu, &qcom_smmu_impl);
544+
match = of_match_node(qcom_smmu_impl_of_match, np);
545+
if (match)
546+
return qcom_smmu_create(smmu, match->data);
476547

477548
return smmu;
478549
}

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h‎

Lines changed: 16 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,26 @@ struct qcom_smmu {
1414
u32 stall_enabled;
1515
};
1616

17+
enum qcom_smmu_impl_reg_offset {
18+
QCOM_SMMU_TBU_PWR_STATUS,
19+
QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
20+
QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
21+
};
22+
23+
struct qcom_smmu_config {
24+
const u32 *reg_offset;
25+
};
26+
27+
struct qcom_smmu_match_data {
28+
const struct qcom_smmu_config *cfg;
29+
const struct arm_smmu_impl *impl;
30+
const struct arm_smmu_impl *adreno_impl;
31+
};
32+
1733
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
1834
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
19-
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
2035
#else
2136
static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
22-
static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
23-
{
24-
return NULL;
25-
}
2637
#endif
2738

2839
#endif /* _ARM_SMMU_QCOM_H */

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