@@ -118,7 +118,6 @@ struct v3d_dev {
118118 void __iomem * core_regs [3 ];
119119 void __iomem * bridge_regs ;
120120 void __iomem * gca_regs ;
121- void __iomem * sms_regs ;
122121 struct clk * clk ;
123122 struct delayed_work clk_down_work ;
124123 unsigned long clk_up_rate , clk_down_rate ;
@@ -275,15 +274,6 @@ to_v3d_fence(struct dma_fence *fence)
275274#define V3D_GCA_READ (offset ) readl(v3d->gca_regs + offset)
276275#define V3D_GCA_WRITE (offset , val ) writel(val, v3d->gca_regs + offset)
277276
278- #define V3D_SMS_IDLE 0x0
279- #define V3D_SMS_ISOLATING_FOR_RESET 0xa
280- #define V3D_SMS_RESETTING 0xb
281- #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc
282- #define V3D_SMS_POWER_OFF_STATE 0xd
283-
284- #define V3D_SMS_READ (offset ) readl(v3d->sms_regs + (offset))
285- #define V3D_SMS_WRITE (offset , val ) writel(val, v3d->sms_regs + (offset))
286-
287277#define V3D_CORE_READ (core , offset ) readl(v3d->core_regs[core] + offset)
288278#define V3D_CORE_WRITE (core , offset , val ) writel(val, v3d->core_regs[core] + offset)
289279
@@ -562,7 +552,6 @@ struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
562552/* v3d_gem.c */
563553int v3d_gem_init (struct drm_device * dev );
564554void v3d_gem_destroy (struct drm_device * dev );
565- void v3d_reset_sms (struct v3d_dev * v3d );
566555void v3d_reset (struct v3d_dev * v3d );
567556void v3d_invalidate_caches (struct v3d_dev * v3d );
568557void v3d_clean_caches (struct v3d_dev * v3d );
0 commit comments