@@ -131,9 +131,11 @@ class SfeAS7331Base {
131131 if (SFE_BUS_OK != _sfeBus->ping (_devSettings))
132132 return false ;
133133
134+ reset ();
135+
134136 if (!isConnected ())
135137 return false ;
136-
138+
137139 if (runSetup)
138140 return runDefaultSetup ();
139141
@@ -238,6 +240,9 @@ class SfeAS7331Base {
238240 if (_state.pd == POWER_DOWN_ENABLE)
239241 if (SFE_BUS_OK != setPowerState (POWER_DOWN_DISABLE)) return false ;
240242
243+ if (_state.opMode != DEVICE_MODE_MEAS)
244+ if (SFE_BUS_OK != setOperationMode (DEVICE_MODE_MEAS)) return false ;
245+
241246 if (_state.mmode != measMode)
242247 {
243248 if (SFE_BUS_OK != setStandbyMode (STANDBY_DISABLED))
@@ -351,19 +356,7 @@ class SfeAS7331Base {
351356 if (SFE_BUS_OK != result)
352357 return result;
353358
354- Serial.print (" Raw values: uvaRaw[1] = 0x" );
355- Serial.print (uvaRaw[1 ], HEX);
356- Serial.print (" , uvaRaw[0] = 0x" );
357- Serial.print (uvaRaw[0 ], HEX);
358- Serial.print (" , uvaRaw[1] << 8 | uvaRaw[0] = " );
359- Serial.print (((uint16_t )uvaRaw[1 ] << 8 | uvaRaw[0 ]), HEX);
360- Serial.print (" , as a float = " );
361- Serial.print ((float )((uint16_t )((uint16_t )uvaRaw[1 ] << 8 | uvaRaw[0 ])), 5 );
362- Serial.print (" , conversionA = " );
363- Serial.print (conversionA);
364- Serial.print (" , measures.uva = " );
365- measures.uva = ((float )((uint16_t )((uint16_t )uvaRaw[1 ] << 8 | uvaRaw[0 ])))*conversionA;
366- Serial.println (measures.uva , 5 );
359+ measures.uva = ((float )((uint16_t )((uint16_t )uvaRaw[1 ] << 8 | uvaRaw[0 ]))-1 .0f )*conversionA;
367360
368361 return SFE_BUS_OK;
369362 }
@@ -378,7 +371,7 @@ class SfeAS7331Base {
378371 if (SFE_BUS_OK != result)
379372 return result;
380373
381- measures.uvb = ((float )((uint16_t )((uint16_t )uvbRaw[1 ] << 8 | uvbRaw[0 ])))*conversionB;
374+ measures.uvb = ((float )((uint16_t )((uint16_t )uvbRaw[1 ] << 8 | uvbRaw[0 ]))- 1 . 0f )*conversionB;
382375
383376 return SFE_BUS_OK;
384377 }
@@ -393,7 +386,7 @@ class SfeAS7331Base {
393386 if (SFE_BUS_OK != result)
394387 return result;
395388
396- measures.uvc = ((float )((uint16_t )((uint16_t )uvcRaw[1 ] << 8 | uvcRaw[0 ])))*conversionC;
389+ measures.uvc = ((float )((uint16_t )((uint16_t )uvcRaw[1 ] << 8 | uvcRaw[0 ]))- 1 . 0f )*conversionC;
397390
398391 return SFE_BUS_OK;
399392 }
@@ -408,9 +401,9 @@ class SfeAS7331Base {
408401 if (SFE_BUS_OK != result)
409402 return result;
410403
411- measures.uva = (float )((uint16_t )(((uint16_t )dataRaw[1 ]) << 8 | dataRaw[0 ]))*conversionA;
412- measures.uvb = (float )((uint16_t )(((uint16_t )dataRaw[3 ]) << 8 | dataRaw[2 ]))*conversionB;
413- measures.uvc = (float )((uint16_t )(((uint16_t )dataRaw[5 ]) << 8 | dataRaw[4 ]))*conversionC;
404+ measures.uva = (float )((uint16_t )(((uint16_t )dataRaw[1 ]) << 8 | dataRaw[0 ])- 1 . 0f )*conversionA;
405+ measures.uvb = (float )((uint16_t )(((uint16_t )dataRaw[3 ]) << 8 | dataRaw[2 ])- 1 . 0f )*conversionB;
406+ measures.uvc = (float )((uint16_t )(((uint16_t )dataRaw[5 ]) << 8 | dataRaw[4 ])- 1 . 0f )*conversionC;
414407
415408 return SFE_BUS_OK;
416409 }
@@ -948,105 +941,90 @@ class SfeAS7331Base {
948941
949942 int8_t getStatus (sfe_as7331_reg_meas_osr_status_t *statusReg)
950943 {
951- // TODO: Add state check
952944 return readRegister (SFE_AS7331_REGISTER_MEAS_OSR_STATUS, statusReg, 2U );
953945 }
954946
955947
956948 int8_t getOSR (sfe_as7331_reg_cfg_osr_t *osrReg)
957949 {
958- // TODO: Add state check
959950 return readRegister (SFE_AS7331_REGISTER_CFG_OSR, &osrReg->byte );
960951 }
961952
962953
963954 int8_t setOSR (const sfe_as7331_reg_cfg_osr_t *osrReg)
964955 {
965- // TODO: Add state check
966956 return writeRegister (SFE_AS7331_REGISTER_CFG_OSR, &osrReg->byte );
967957 }
968958
969959
970960 int8_t getCReg1 (sfe_as7331_reg_cfg_creg1_t *creg1)
971961 {
972- // TODO: Add state check
973962 return readRegister (SFE_AS7331_REGISTER_CFG_CREG1, &creg1->byte );
974963 }
975964
976965
977966 int8_t setCReg1 (const sfe_as7331_reg_cfg_creg1_t *creg1)
978967 {
979- // TODO: Add state check
980968 return writeRegister (SFE_AS7331_REGISTER_CFG_CREG1, &creg1->byte );
981969 }
982970
983971
984972 int8_t getCReg2 (sfe_as7331_reg_cfg_creg2_t *creg2)
985973 {
986- // TODO: Add state check
987974 return readRegister (SFE_AS7331_REGISTER_CFG_CREG2, &creg2->byte );
988975 }
989976
990977
991978 int8_t setCReg2 (const sfe_as7331_reg_cfg_creg2_t *creg2)
992979 {
993- // TODO: Add state check
994980 return writeRegister (SFE_AS7331_REGISTER_CFG_CREG2, &creg2->byte );
995981 }
996982
997983
998984 int8_t getCReg3 (sfe_as7331_reg_cfg_creg3_t *creg3)
999985 {
1000- // TODO: Add state check
1001986 return readRegister (SFE_AS7331_REGISTER_CFG_CREG3, &creg3->byte );
1002987 }
1003988
1004989
1005990 int8_t setCReg3 (const sfe_as7331_reg_cfg_creg3_t *creg3)
1006991 {
1007- // TODO: Add state check
1008992 return writeRegister (SFE_AS7331_REGISTER_CFG_CREG3, &creg3->byte );
1009993 }
1010994
1011995
1012996 int8_t getBreak (sfe_as7331_reg_cfg_break_t *breakReg)
1013997 {
1014- // TODO: Add state check
1015998 return readRegister (SFE_AS7331_REGISTER_CFG_BREAK, breakReg);
1016999 }
10171000
10181001
10191002 int8_t setBreak (const sfe_as7331_reg_cfg_break_t *breakReg)
10201003 {
1021- // TODO: Add state check
10221004 return writeRegister (SFE_AS7331_REGISTER_CFG_BREAK, breakReg);
10231005 }
10241006
10251007
10261008 int8_t getEdges (sfe_as7331_reg_cfg_edges_t *edgesReg)
10271009 {
1028- // TODO: Add state check
10291010 return readRegister (SFE_AS7331_REGISTER_CFG_EDGES, edgesReg);
10301011 }
10311012
10321013
10331014 int8_t setEdges (const sfe_as7331_reg_cfg_edges_t *edgesReg)
10341015 {
1035- // TODO: Add state check
10361016 return writeRegister (SFE_AS7331_REGISTER_CFG_EDGES, edgesReg);
10371017 }
10381018
10391019
10401020 int8_t getOptIndex (sfe_as7331_reg_cfg_optreg_t *optReg)
10411021 {
1042- // TODO: Add state check
10431022 return readRegister (SFE_AS7331_REGISTER_CFG_OPTREG, &optReg->byte );
10441023 }
10451024
10461025
10471026 int8_t setOptIndex (const sfe_as7331_reg_cfg_optreg_t *optReg)
10481027 {
1049- // TODO: Add state check
10501028 return writeRegister (SFE_AS7331_REGISTER_CFG_OPTREG, &optReg->byte );
10511029 }
10521030
0 commit comments