soc: nxp/mcxn: Add power management support for MCXN236

Add power management support for MCXN/MCXN236.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>

Author: ZhaoxiangJin

soc/nxp/mcx/mcxn/CMakeLists.txt

@@ -37,3 +37,5 @@ set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/li
 
 # Build the SoC P-state setter implementation for CPUFreq when selected
 zephyr_library_sources_ifdef(CONFIG_CPU_FREQ_PSTATE_SET_SOC cpu_freq_scale.c)
+
+zephyr_sources_ifdef(CONFIG_PM power.c)

soc/nxp/mcx/mcxn/Kconfig

@@ -44,6 +44,7 @@ config SOC_MCXN236
 	select SOC_RESET_HOOK
 	select ARM_TRUSTZONE_M
 	select HAS_CPU_FREQ
+	select HAS_PM
 
 if SOC_FAMILY_MCXN
 

soc/nxp/mcx/mcxn/Kconfig.defconfig

@@ -37,4 +37,11 @@ config FLASH_FILL_BUFFER_SIZE
 config I2S_HAS_PLL_SETTING
 	default n
 
+if PM
+
+configdefault CORTEX_M_SYSTICK_RESET_BY_LPM
+	default y
+
+endif # PM
+
 endif # SOC_FAMILY_MCXN

soc/nxp/mcx/mcxn/power.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/pm/pm.h>
+#include <zephyr/device.h>
+#include <fsl_cmc.h>
+#include <fsl_spc.h>
+#include <fsl_wuu.h>
+
+#define WUU_WAKEUP_LPTMR0_IDX	6U
+#define MCXN_WAKEUP_DELAY	DT_PROP_OR(DT_NODELABEL(spc), wakeup_delay, 0)
+#define MCXN_WUU_ADDR		(WUU_Type *)DT_REG_ADDR(DT_INST(0, nxp_wuu))
+#define MCXN_CMC_ADDR		(CMC_Type *)DT_REG_ADDR(DT_INST(0, nxp_cmc))
+#define MCXN_SPC_ADDR		(SPC_Type *)DT_REG_ADDR(DT_INST(0, nxp_spc))
+
+static void pm_enter_hook(void)
+{
+	CMC_SetPowerModeProtection(MCXN_CMC_ADDR, kCMC_AllowAllLowPowerModes);
+	CMC_EnableDebugOperation(MCXN_CMC_ADDR, false);
+	CMC_ConfigFlashMode(MCXN_CMC_ADDR, true, false);
+	WUU_SetInternalWakeUpModulesConfig(MCXN_WUU_ADDR, WUU_WAKEUP_LPTMR0_IDX,
+					kWUU_InternalModuleInterrupt);
+}
+
+__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	pm_enter_hook();
+
+	__enable_irq();
+	__set_BASEPRI(0);
+
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		CMC_SetClockMode(MCXN_CMC_ADDR, kCMC_GateCoreClock);
+		CMC_SetMAINPowerMode(MCXN_CMC_ADDR, kCMC_ActiveOrSleepMode);
+		CMC_SetWAKEPowerMode(MCXN_CMC_ADDR, kCMC_ActiveOrSleepMode);
+		__WFI();
+		break;
+
+	case PM_STATE_SUSPEND_TO_IDLE:
+		CMC_SetClockMode(MCXN_CMC_ADDR, kCMC_GateAllSystemClocksEnterLowPowerMode);
+		CMC_SetMAINPowerMode(MCXN_CMC_ADDR, kCMC_DeepSleepMode);
+		CMC_SetWAKEPowerMode(MCXN_CMC_ADDR, kCMC_DeepSleepMode);
+		__WFI();
+		break;
+
+	case PM_STATE_STANDBY:
+		SPC_SetLowPowerWakeUpDelay(SPC0, MCXN_WAKEUP_DELAY);
+		CMC_SetClockMode(MCXN_CMC_ADDR, kCMC_GateAllSystemClocksEnterLowPowerMode);
+		CMC_SetMAINPowerMode(MCXN_CMC_ADDR, kCMC_PowerDownMode);
+		CMC_SetWAKEPowerMode(MCXN_CMC_ADDR, kCMC_PowerDownMode);
+		__WFI();
+		break;
+
+	default:
+		break;
+	}
+}
+
+__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(state);
+	ARG_UNUSED(substate_id);
+
+	if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
+		SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+	}
+
+	__enable_irq();
+	__ISB();
+
+	SPC_ClearPowerDomainLowPowerRequestFlag(MCXN_SPC_ADDR, kSPC_PowerDomain0);
+	SPC_ClearPowerDomainLowPowerRequestFlag(MCXN_SPC_ADDR, kSPC_PowerDomain1);
+	SPC_ClearLowPowerRequest(MCXN_SPC_ADDR);
+}