Pytest modules for dataflow analyzer are added.

Author: shtaxxx

testcode/__init__.py

@@ -1,4 +1,3 @@
-
 module TOP(CLK, RST_X, IN, OUT);
   input CLK, RST_X;
   input [7:0] IN;
@@ -54,6 +53,4 @@ module TOP(CLK, RST_X, IN, OUT);
   end
 
 endmodule
-  
 
-  

testcode/blocking.v

@@ -1,6 +1,5 @@
-module TOP(CLK, RST, LED);
+module TOP(CLK, RST);
   input CLK, RST;
-  output [7:0] LED;
   reg [7:0] cnt;
   always @(posedge CLK) begin
     if(RST) begin
@@ -19,6 +18,4 @@ module TOP(CLK, RST, LED);
       endcase
     end
   end
-  assign LED = cnt;
 endmodule
-

testcode/case.v

@@ -1,6 +1,5 @@
-module TOP(CLK, RST, LED);
+module TOP(CLK, RST);
   input CLK, RST;
-  output [7:0] LED;
   reg [7:0] cnt;
   always @(posedge CLK) begin
     if(RST) begin
@@ -19,6 +18,4 @@ module TOP(CLK, RST, LED);
       endcase
     end
   end
-  assign LED = cnt;
 endmodule
-

testcode/casex.v

@@ -1,18 +1,14 @@
-module TOP(CLK, RST_X, LED);
+module TOP(CLK, RST_X);
   input CLK;
   input RST_X;
-  output LED;
-
   reg [3:0] cnt;
 
-  assign LED = cnt[3];
-
   always @(posedge CLK or negedge RST_X) begin
     if(!RST_X) begin
       cnt <= 0;
     end else begin
       cnt <= cnt + 1;
     end
   end
-
+  
 endmodule

testcode/count.v

@@ -1,19 +1,13 @@
-//`default_nettype none
-
 module TOP(CLK, RST);
   input CLK, RST;
-  reg [7:0] cnt1;
-
+  reg [7:0] cnt;
 
   always @(posedge CLK or negedge RST) begin
     if(RST) begin
-      cnt1 <= 'd0;
+      cnt <= 'd0;
     end else begin
-      cnt1 <= cnt1 + 8'd1;
+      cnt <= cnt + 'd1;
     end
   end
 
-
-
 endmodule
-

testcode/decimal.v

@@ -1,10 +1,7 @@
-//`default_nettype none
-
 module TOP(CLK, RST);
   input CLK, RST;
   reg [7:0] cnt;
 
-
   always @(posedge CLK or negedge RST) begin
     if(RST) begin
       cnt <= 'd0;
@@ -13,6 +10,4 @@ module TOP(CLK, RST);
     end
   end
 
-
 endmodule
-

testcode/signed.v testcode/decimal_signed.vtestcode/signed.v renamed to testcode/decimal_signed.v

@@ -1,18 +1,13 @@
-//`default_nettype none
-
 module TOP(CLK, RST);
   input CLK, RST;
-  reg [7:0] cnt2;
-
-
+  reg [7:0] cnt;
+  
   always @(posedge CLK or negedge RST) begin
     if(RST) begin
-      cnt2 <= 'd0;
+      cnt <= 'd0;
     end else begin
-      cnt2 <= cnt2 + 'd1;
+      cnt <= cnt + 8'd1;
     end
   end
 
-
 endmodule
-

testcode/decimal2.v testcode/decimal_width.vtestcode/decimal2.v renamed to testcode/decimal_width.v

@@ -1,118 +1,112 @@
-module TOP(CLK, RST, LED);
+module TOP(CLK, RST);
   input CLK, RST;
-  output [7:0] LED;
   reg [31:0] cnt;
   always @(posedge CLK) begin
     if(RST) begin
       cnt <= 0;
     end else begin
-
       case(cnt)
-
-0 : begin
-cnt <= 0 + 1;
-end
-1 : begin
-cnt <= 1 + 1;
-end
-2 : begin
-cnt <= 2 + 1;
-end
-3 : begin
-cnt <= 3 + 1;
-end
-4 : begin
-cnt <= 4 + 1;
-end
-5 : begin
-cnt <= 5 + 1;
-end
-6 : begin
-cnt <= 6 + 1;
-end
-7 : begin
-cnt <= 7 + 1;
-end
-8 : begin
-cnt <= 8 + 1;
-end
-9 : begin
-cnt <= 9 + 1;
-end
-10 : begin
-cnt <= 10 + 1;
-end
-11 : begin
-cnt <= 11 + 1;
-end
-12 : begin
-cnt <= 12 + 1;
-end
-13 : begin
-cnt <= 13 + 1;
-end
-14 : begin
-cnt <= 14 + 1;
-end
-15 : begin
-cnt <= 15 + 1;
-end
-16 : begin
-cnt <= 16 + 1;
-end
-17 : begin
-cnt <= 17 + 1;
-end
-18 : begin
-cnt <= 18 + 1;
-end
-19 : begin
-cnt <= 19 + 1;
-end
-20 : begin
-cnt <= 20 + 1;
-end
-21 : begin
-cnt <= 21 + 1;
-end
-22 : begin
-cnt <= 22 + 1;
-end
-23 : begin
-cnt <= 23 + 1;
-end
-24 : begin
-cnt <= 24 + 1;
-end
-25 : begin
-cnt <= 25 + 1;
-end
-26 : begin
-cnt <= 26 + 1;
-end
-27 : begin
-cnt <= 27 + 1;
-end
-28 : begin
-cnt <= 28 + 1;
-end
-29 : begin
-cnt <= 29 + 1;
-end
-30 : begin
-cnt <= 30 + 1;
-end
-31 : begin
-cnt <= 31 + 1;
-end
+        0 : begin
+          cnt <= 0 + 1;
+        end
+        1 : begin
+          cnt <= 1 + 1;
+        end
+        2 : begin
+          cnt <= 2 + 1;
+        end
+        3 : begin
+          cnt <= 3 + 1;
+        end
+        4 : begin
+          cnt <= 4 + 1;
+        end
+        5 : begin
+          cnt <= 5 + 1;
+        end
+        6 : begin
+          cnt <= 6 + 1;
+        end
+        7 : begin
+          cnt <= 7 + 1;
+        end
+        8 : begin
+          cnt <= 8 + 1;
+        end
+        9 : begin
+          cnt <= 9 + 1;
+        end
+        10 : begin
+          cnt <= 10 + 1;
+        end
+        11 : begin
+          cnt <= 11 + 1;
+        end
+        12 : begin
+          cnt <= 12 + 1;
+        end
+        13 : begin
+          cnt <= 13 + 1;
+        end
+        14 : begin
+          cnt <= 14 + 1;
+        end
+        15 : begin
+          cnt <= 15 + 1;
+        end
+        16 : begin
+          cnt <= 16 + 1;
+        end
+        17 : begin
+          cnt <= 17 + 1;
+        end
+        18 : begin
+          cnt <= 18 + 1;
+        end
+        19 : begin
+          cnt <= 19 + 1;
+        end
+        20 : begin
+          cnt <= 20 + 1;
+        end
+        21 : begin
+          cnt <= 21 + 1;
+        end
+        22 : begin
+          cnt <= 22 + 1;
+        end
+        23 : begin
+          cnt <= 23 + 1;
+        end
+        24 : begin
+          cnt <= 24 + 1;
+        end
+        25 : begin
+          cnt <= 25 + 1;
+        end
+        26 : begin
+          cnt <= 26 + 1;
+        end
+        27 : begin
+          cnt <= 27 + 1;
+        end
+        28 : begin
+          cnt <= 28 + 1;
+        end
+        29 : begin
+          cnt <= 29 + 1;
+        end
+        30 : begin
+          cnt <= 30 + 1;
+        end
+        31 : begin
+          cnt <= 31 + 1;
+        end
         default: begin
           cnt <= cnt + 1;
         end
-
       endcase
-
     end
   end
-  assign LED = cnt;
 endmodule