New parser test is added

Author: shtaxxx

test/parser_test/Makefile

@@ -1,19 +1,10 @@
-TEST=test.py
-ARGS=
-
-PYTHON=python3
-#PYTHON=python
-#OPT=-m pdb
-#OPT=-m cProfile -s time
-#OPT=-m cProfile -o profile.rslt
-
 .PHONY: all
-all: test
+all: clean
 
 .PHONY: test
 test:
-	$(PYTHON) -m pytest -vv $(TEST)
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {} 
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 

test/parser_test/delay/Makefile

@@ -0,0 +1,19 @@
+TEST=test.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

test/parser_test/delay/main.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+
+module main #
+(
+ parameter STEP = 10
+)
+(
+ input CLK,
+ input RST,
+ output reg [7:0] LED
+ );
+
+  localparam DELAY = 10;
+  
+  reg [31:0] count;
+  
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+      LED <= 0;
+    end else begin
+      if(count == STEP - 1) begin
+        count <= 0;
+        LED <= #DELAY LED + 1;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+endmodule

test/parser_test/delay/pyverilog

@@ -0,0 +1 @@
+../../../pyverilog

test/parser_test/delay/test.py

@@ -0,0 +1,119 @@
+import os
+import sys
+from pyverilog.vparser.parser import VerilogCodeParser
+
+try:
+    from StringIO import StringIO
+except:
+    from io import StringIO
+
+expected = """\
+Source: 
+  Description: 
+    ModuleDef: main
+      Paramlist: 
+        Decl: 
+          Parameter: STEP, False
+            Rvalue: 
+              IntConst: 10
+      Portlist: 
+        Ioport: 
+          Input: CLK, False
+            Width: 
+              IntConst: 0
+              IntConst: 0
+        Ioport: 
+          Input: RST, False
+            Width: 
+              IntConst: 0
+              IntConst: 0
+        Ioport: 
+          Output: LED, False
+            Width: 
+              IntConst: 7
+              IntConst: 0
+          Reg: LED, False
+            Width: 
+              IntConst: 7
+              IntConst: 0
+      Decl: 
+        Localparam: DELAY, False
+          Rvalue: 
+            IntConst: 10
+      Decl: 
+        Reg: count, False
+          Width: 
+            IntConst: 31
+            IntConst: 0
+      Always: 
+        SensList: 
+          Sens: posedge
+            Identifier: CLK
+        Block: None
+          IfStatement: 
+            Identifier: RST
+            Block: None
+              NonblockingSubstitution: 
+                Lvalue: 
+                  Identifier: count
+                Rvalue: 
+                  IntConst: 0
+              NonblockingSubstitution: 
+                Lvalue: 
+                  Identifier: LED
+                Rvalue: 
+                  IntConst: 0
+            Block: None
+              IfStatement: 
+                Eq: 
+                  Identifier: count
+                  Minus: 
+                    Identifier: STEP
+                    IntConst: 1
+                Block: None
+                  NonblockingSubstitution: 
+                    Lvalue: 
+                      Identifier: count
+                    Rvalue: 
+                      IntConst: 0
+                  NonblockingSubstitution: 
+                    Lvalue: 
+                      Identifier: LED
+                    Rvalue: 
+                      Plus: 
+                        Identifier: LED
+                        IntConst: 1
+                    DelayStatement: 
+                      Identifier: DELAY
+                Block: None
+                  NonblockingSubstitution: 
+                    Lvalue: 
+                      Identifier: count
+                    Rvalue: 
+                      Plus: 
+                        Identifier: count
+                        IntConst: 1
+Line 1 : `timescale 1ns / 1ps
+"""
+
+def test():
+    filelist = ['main.v']
+    output = 'preprocess.out'
+    include = None
+    define = None
+    
+    parser = VerilogCodeParser(filelist,
+                               preprocess_include=include,
+                               preprocess_define=define)
+    ast = parser.parse()
+    directives = parser.get_directives()
+
+    output = StringIO()
+    ast.show(buf=output)
+
+    for lineno, directive in directives:
+        output.write('Line %d : %s' % (lineno, directive))
+    
+    rslt = output.getvalue()
+
+    assert(rslt == expected)

test/parser_test/led/Makefile

@@ -0,0 +1,19 @@
+TEST=test.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

test/parser_test/led.v test/parser_test/led/led.vtest/parser_test/led.v renamed to test/parser_test/led/led.v

@@ -0,0 +1 @@
+../../../pyverilog