URL

Author: shtaxxx

README.md

@@ -365,15 +365,14 @@ endmodule
 Related Project and Site
 ==============================
 
-[PyCoRAM](http://shtaxxx.github.io/PyCoRAM/)
+[PyCoRAM](https://github.com/shtaxxx/PyCoRAM)
 - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
 
-[flipSyrup](http://shtaxxx.github.io/flipSyrup/)
+[flipSyrup](https://github.com/shtaxxx/flipSyrup)
 - Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms
 
 [Pyverilog_toolbox](https://github.com/fukatani/Pyverilog_toolbox)
 - Pyverilog_toolbox is Pyverilog-based verification/design tool, which is developed by Fukatani-san and uses Pyverilog as a fundamental library. Thanks for your contribution!
 
 [shtaxxx.hatenablog.com](http://shtaxxx.hatenablog.com/entry/2014/01/01/045856)
 - Blog entry for introduction and examples of Pyverilog (in Japansese)
-

pages.md

@@ -351,10 +351,10 @@ endmodule
 Related Project and Site
 ==============================
 
-[PyCoRAM](http://shtaxxx.github.io/PyCoRAM/)
+[PyCoRAM](https://github.com/shtaxxx/PyCoRAM)
 - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
 
-[flipSyrup](http://shtaxxx.github.io/flipSyrup/)
+[flipSyrup](https://github.com/shtaxxx/flipSyrup)
 - Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms
 
 [Pyverilog_toolbox](https://github.com/fukatani/Pyverilog_toolbox)