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Jakub Ramaseuski
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RDMA/ionic: Create device queues to support admin operations
JIRA: https://issues.redhat.com/browse/RHEL-121486 commit f3bdbd4 Author: Abhijit Gangurde <abhijit.gangurde@amd.com> Date: Wed Sep 3 11:46:01 2025 +0530 RDMA/ionic: Create device queues to support admin operations Setup RDMA admin queues using device command exposed over auxiliary device and manage these queues using ida. Co-developed-by: Andrew Boyer <andrew.boyer@amd.com> Signed-off-by: Andrew Boyer <andrew.boyer@amd.com> Co-developed-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com> Link: https://patch.msgid.link/20250903061606.4139957-10-abhijit.gangurde@amd.com Signed-off-by: Leon Romanovsky <leon@kernel.org> Signed-off-by: Jakub Ramaseuski <jramaseu@redhat.com>
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‎drivers/infiniband/hw/ionic/ionic_admin.c‎

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‎drivers/infiniband/hw/ionic/ionic_controlpath.c‎

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// SPDX-License-Identifier: GPL-2.0
2+
/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */
3+
4+
#include "ionic_ibdev.h"
5+
6+
static int ionic_validate_qdesc(struct ionic_qdesc *q)
7+
{
8+
if (!q->addr || !q->size || !q->mask ||
9+
!q->depth_log2 || !q->stride_log2)
10+
return -EINVAL;
11+
12+
if (q->addr & (PAGE_SIZE - 1))
13+
return -EINVAL;
14+
15+
if (q->mask != BIT(q->depth_log2) - 1)
16+
return -EINVAL;
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18+
if (q->size < BIT_ULL(q->depth_log2 + q->stride_log2))
19+
return -EINVAL;
20+
21+
return 0;
22+
}
23+
24+
static u32 ionic_get_eqid(struct ionic_ibdev *dev, u32 comp_vector, u8 udma_idx)
25+
{
26+
/* EQ per vector per udma, and the first eqs reserved for async events.
27+
* The rest of the vectors can be requested for completions.
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*/
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u32 comp_vec_count = dev->lif_cfg.eq_count / dev->lif_cfg.udma_count - 1;
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return (comp_vector % comp_vec_count + 1) * dev->lif_cfg.udma_count + udma_idx;
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}
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static int ionic_get_cqid(struct ionic_ibdev *dev, u32 *cqid, u8 udma_idx)
35+
{
36+
unsigned int size, base, bound;
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int rc;
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size = dev->lif_cfg.cq_count / dev->lif_cfg.udma_count;
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base = size * udma_idx;
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bound = base + size;
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rc = ionic_resid_get_shared(&dev->inuse_cqid, base, bound);
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if (rc >= 0) {
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/* cq_base is zero or a multiple of two queue groups */
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*cqid = dev->lif_cfg.cq_base +
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ionic_bitid_to_qid(rc, dev->lif_cfg.udma_qgrp_shift,
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dev->half_cqid_udma_shift);
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rc = 0;
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}
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return rc;
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}
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static void ionic_put_cqid(struct ionic_ibdev *dev, u32 cqid)
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{
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u32 bitid = ionic_qid_to_bitid(cqid - dev->lif_cfg.cq_base,
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dev->lif_cfg.udma_qgrp_shift,
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dev->half_cqid_udma_shift);
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ionic_resid_put(&dev->inuse_cqid, bitid);
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}
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int ionic_create_cq_common(struct ionic_vcq *vcq,
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struct ionic_tbl_buf *buf,
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const struct ib_cq_init_attr *attr,
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struct ionic_ctx *ctx,
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struct ib_udata *udata,
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struct ionic_qdesc *req_cq,
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__u32 *resp_cqid,
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int udma_idx)
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{
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struct ionic_ibdev *dev = to_ionic_ibdev(vcq->ibcq.device);
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struct ionic_cq *cq = &vcq->cq[udma_idx];
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void *entry;
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int rc;
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cq->vcq = vcq;
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if (attr->cqe < 1 || attr->cqe + IONIC_CQ_GRACE > 0xffff) {
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rc = -EINVAL;
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goto err_args;
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}
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rc = ionic_get_cqid(dev, &cq->cqid, udma_idx);
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if (rc)
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goto err_args;
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cq->eqid = ionic_get_eqid(dev, attr->comp_vector, udma_idx);
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spin_lock_init(&cq->lock);
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INIT_LIST_HEAD(&cq->poll_sq);
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INIT_LIST_HEAD(&cq->flush_sq);
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INIT_LIST_HEAD(&cq->flush_rq);
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if (udata) {
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rc = ionic_validate_qdesc(req_cq);
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if (rc)
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goto err_qdesc;
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cq->umem = ib_umem_get(&dev->ibdev, req_cq->addr, req_cq->size,
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IB_ACCESS_LOCAL_WRITE);
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if (IS_ERR(cq->umem)) {
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rc = PTR_ERR(cq->umem);
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goto err_qdesc;
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}
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cq->q.ptr = NULL;
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cq->q.size = req_cq->size;
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cq->q.mask = req_cq->mask;
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cq->q.depth_log2 = req_cq->depth_log2;
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cq->q.stride_log2 = req_cq->stride_log2;
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*resp_cqid = cq->cqid;
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} else {
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rc = ionic_queue_init(&cq->q, dev->lif_cfg.hwdev,
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attr->cqe + IONIC_CQ_GRACE,
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sizeof(struct ionic_v1_cqe));
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if (rc)
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goto err_q_init;
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ionic_queue_dbell_init(&cq->q, cq->cqid);
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cq->color = true;
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cq->credit = cq->q.mask;
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}
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rc = ionic_pgtbl_init(dev, buf, cq->umem, cq->q.dma, 1, PAGE_SIZE);
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if (rc)
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goto err_pgtbl_init;
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init_completion(&cq->cq_rel_comp);
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kref_init(&cq->cq_kref);
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entry = xa_store_irq(&dev->cq_tbl, cq->cqid, cq, GFP_KERNEL);
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if (entry) {
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if (!xa_is_err(entry))
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rc = -EINVAL;
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else
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rc = xa_err(entry);
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goto err_xa;
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}
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return 0;
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err_xa:
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ionic_pgtbl_unbuf(dev, buf);
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err_pgtbl_init:
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if (!udata)
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ionic_queue_destroy(&cq->q, dev->lif_cfg.hwdev);
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err_q_init:
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if (cq->umem)
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ib_umem_release(cq->umem);
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err_qdesc:
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ionic_put_cqid(dev, cq->cqid);
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err_args:
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cq->vcq = NULL;
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return rc;
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}
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void ionic_destroy_cq_common(struct ionic_ibdev *dev, struct ionic_cq *cq)
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{
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if (!cq->vcq)
166+
return;
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xa_erase_irq(&dev->cq_tbl, cq->cqid);
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kref_put(&cq->cq_kref, ionic_cq_complete);
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wait_for_completion(&cq->cq_rel_comp);
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if (cq->umem)
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ib_umem_release(cq->umem);
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else
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ionic_queue_destroy(&cq->q, dev->lif_cfg.hwdev);
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ionic_put_cqid(dev, cq->cqid);
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cq->vcq = NULL;
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}

‎drivers/infiniband/hw/ionic/ionic_fw.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */
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#ifndef _IONIC_FW_H_
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#define _IONIC_FW_H_
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#include <linux/kernel.h>
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/* completion queue v1 cqe */
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struct ionic_v1_cqe {
11+
union {
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struct {
13+
__be16 cmd_idx;
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__u8 cmd_op;
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__u8 rsvd[17];
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__le16 old_sq_cindex;
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__le16 old_rq_cq_cindex;
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} admin;
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struct {
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__u64 wqe_id;
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__be32 src_qpn_op;
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__u8 src_mac[6];
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__be16 vlan_tag;
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__be32 imm_data_rkey;
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} recv;
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struct {
27+
__u8 rsvd[4];
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__be32 msg_msn;
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__u8 rsvd2[8];
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__u64 npg_wqe_id;
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} send;
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};
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__be32 status_length;
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__be32 qid_type_flags;
35+
};
36+
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/* bits for cqe qid_type_flags */
38+
enum ionic_v1_cqe_qtf_bits {
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IONIC_V1_CQE_COLOR = BIT(0),
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IONIC_V1_CQE_ERROR = BIT(1),
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IONIC_V1_CQE_TYPE_SHIFT = 5,
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IONIC_V1_CQE_TYPE_MASK = 0x7,
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IONIC_V1_CQE_QID_SHIFT = 8,
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IONIC_V1_CQE_TYPE_ADMIN = 0,
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IONIC_V1_CQE_TYPE_RECV = 1,
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IONIC_V1_CQE_TYPE_SEND_MSN = 2,
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IONIC_V1_CQE_TYPE_SEND_NPG = 3,
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};
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static inline bool ionic_v1_cqe_color(struct ionic_v1_cqe *cqe)
52+
{
53+
return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_COLOR);
54+
}
55+
56+
static inline bool ionic_v1_cqe_error(struct ionic_v1_cqe *cqe)
57+
{
58+
return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_ERROR);
59+
}
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61+
static inline void ionic_v1_cqe_clean(struct ionic_v1_cqe *cqe)
62+
{
63+
cqe->qid_type_flags |= cpu_to_be32(~0u << IONIC_V1_CQE_QID_SHIFT);
64+
}
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static inline u32 ionic_v1_cqe_qtf(struct ionic_v1_cqe *cqe)
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{
68+
return be32_to_cpu(cqe->qid_type_flags);
69+
}
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static inline u8 ionic_v1_cqe_qtf_type(u32 qtf)
72+
{
73+
return (qtf >> IONIC_V1_CQE_TYPE_SHIFT) & IONIC_V1_CQE_TYPE_MASK;
74+
}
75+
76+
static inline u32 ionic_v1_cqe_qtf_qid(u32 qtf)
77+
{
78+
return qtf >> IONIC_V1_CQE_QID_SHIFT;
79+
}
80+
81+
#define ADMIN_WQE_STRIDE 64
82+
#define ADMIN_WQE_HDR_LEN 4
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84+
/* admin queue v1 wqe */
85+
struct ionic_v1_admin_wqe {
86+
__u8 op;
87+
__u8 rsvd;
88+
__le16 len;
89+
90+
union {
91+
} cmd;
92+
};
93+
94+
/* admin queue v1 cqe status */
95+
enum ionic_v1_admin_status {
96+
IONIC_V1_ASTS_OK,
97+
IONIC_V1_ASTS_BAD_CMD,
98+
IONIC_V1_ASTS_BAD_INDEX,
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IONIC_V1_ASTS_BAD_STATE,
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IONIC_V1_ASTS_BAD_TYPE,
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IONIC_V1_ASTS_BAD_ATTR,
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IONIC_V1_ASTS_MSG_TOO_BIG,
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};
104+
105+
/* event queue v1 eqe */
106+
struct ionic_v1_eqe {
107+
__be32 evt;
108+
};
109+
110+
/* bits for cqe queue_type_flags */
111+
enum ionic_v1_eqe_evt_bits {
112+
IONIC_V1_EQE_COLOR = BIT(0),
113+
IONIC_V1_EQE_TYPE_SHIFT = 1,
114+
IONIC_V1_EQE_TYPE_MASK = 0x7,
115+
IONIC_V1_EQE_CODE_SHIFT = 4,
116+
IONIC_V1_EQE_CODE_MASK = 0xf,
117+
IONIC_V1_EQE_QID_SHIFT = 8,
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119+
/* cq events */
120+
IONIC_V1_EQE_TYPE_CQ = 0,
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/* cq normal events */
122+
IONIC_V1_EQE_CQ_NOTIFY = 0,
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/* cq error events */
124+
IONIC_V1_EQE_CQ_ERR = 8,
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126+
/* qp and srq events */
127+
IONIC_V1_EQE_TYPE_QP = 1,
128+
/* qp normal events */
129+
IONIC_V1_EQE_SRQ_LEVEL = 0,
130+
IONIC_V1_EQE_SQ_DRAIN = 1,
131+
IONIC_V1_EQE_QP_COMM_EST = 2,
132+
IONIC_V1_EQE_QP_LAST_WQE = 3,
133+
/* qp error events */
134+
IONIC_V1_EQE_QP_ERR = 8,
135+
IONIC_V1_EQE_QP_ERR_REQUEST = 9,
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IONIC_V1_EQE_QP_ERR_ACCESS = 10,
137+
};
138+
139+
static inline bool ionic_v1_eqe_color(struct ionic_v1_eqe *eqe)
140+
{
141+
return eqe->evt & cpu_to_be32(IONIC_V1_EQE_COLOR);
142+
}
143+
144+
static inline u32 ionic_v1_eqe_evt(struct ionic_v1_eqe *eqe)
145+
{
146+
return be32_to_cpu(eqe->evt);
147+
}
148+
149+
static inline u8 ionic_v1_eqe_evt_type(u32 evt)
150+
{
151+
return (evt >> IONIC_V1_EQE_TYPE_SHIFT) & IONIC_V1_EQE_TYPE_MASK;
152+
}
153+
154+
static inline u8 ionic_v1_eqe_evt_code(u32 evt)
155+
{
156+
return (evt >> IONIC_V1_EQE_CODE_SHIFT) & IONIC_V1_EQE_CODE_MASK;
157+
}
158+
159+
static inline u32 ionic_v1_eqe_evt_qid(u32 evt)
160+
{
161+
return evt >> IONIC_V1_EQE_QID_SHIFT;
162+
}
163+
164+
#endif /* _IONIC_FW_H_ */

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