ARC-V RHX-100 upstream patch series #192

MichielDerhaeg · 2025-11-28T20:05:47Z

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The Synopsys RMX-100 has a short, three-stage, in-order execution pipeline. The option -mmpy-option was added to control which version of the MPY unit the core has and what the latency of multiply instructions should be similar to ARCv2 cores (see gcc/config/arc/arc.opt:60). Authored-by: Artemiy Volkov <artemiy@synopsys.com> Signed-off-by: Michiel Derhaeg <michiel@synopsys.com>

The Synopsys RHX-100 has a 10-stage, dual-issue, in-order execution pipeline. It has support for instruction fusion, which will be addressed by subsequent patches.

…eries

…axt fusion

MichielDerhaeg

I tried to split up the commits in something sensible. Didn't check whether they can be built individually though.

MichielDerhaeg · 2025-11-28T20:07:38Z

gcc/config/riscv/riscv.cc

  return store_data_bypass_p (out_insn, in_insn);
 }

-/* Implement one boolean function for each of the values of the


Should the declarations in the header be moved to arcv.h?

I know I originally placed the declarations in arcv.h, but looking at the existing code structure, it may be a better fit to keep them in riscv-protos.h

EDIT: See d479345

gcc/config/riscv/riscv-protos.h

MichielDerhaeg · 2025-11-28T20:10:29Z

gcc/config/riscv/riscv.cc

    case SIGN_EXTRACT:
-      if (TARGET_XTHEADBB && outer_code == SET
+      if ((TARGET_ARCV_RHX100 || TARGET_XTHEADBB)
+	  && outer_code == SET


FYI, this was added for the bit-extract fusion.

MichielDerhaeg · 2025-11-28T20:11:10Z

gcc/config/riscv/riscv.md

+(define_insn "*zero_extract_fused"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_operand 2 "const_int_operand")
+			 (match_operand 3 "const_int_operand")))]
+  "TARGET_ARCV_RHX100 && !TARGET_64BIT
+     && (INTVAL (operands[2]) > 1 || !TARGET_ZBS)"
+  {
+     int amount = INTVAL (operands[2]);
+     int end = INTVAL (operands[3]) + amount;
+     operands[2] = GEN_INT (BITS_PER_WORD - end);
+     operands[3] = GEN_INT (BITS_PER_WORD - amount);
+     return "slli\t%0,%1,%2\n\tsrli\t%0,%0,%3";
+  }
+  [(set_attr "type" "alu_fused")]
+)


As far as I can tell, this fusion was never implemented as a define_insn_and_split. Might not be trivial to force these exact instructions after a split.

MichielDerhaeg · 2025-11-28T20:13:29Z

gcc/config/riscv/riscv.md

+(define_insn "madd_split_fused"
+  [(set (match_operand:SI 0 "register_operand" "=&r,r")
+     (plus:SI
+	(mult:SI (match_operand:SI 1 "register_operand" "r,r")
+		 (match_operand:SI 2 "register_operand" "r,r"))
+	(match_operand:SI 3 "register_operand" "r,?0")))
+    (clobber (match_scratch:SI 4 "=&r,&r"))]
+  "TARGET_ARCV_RHX100
+   && !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL)"
+  {
+     if (REGNO (operands[0]) == REGNO (operands[3]))
+       {
+	 return "mul\t%4,%1,%2\n\tadd\t%4,%3,%4\n\tmv\t%0,%4";
+       }
+     else
+       {
+	 return "mul\t%0,%1,%2\n\tadd\t%0,%0,%3";
+       }
+  }
+  [(set_attr "type" "imul_fused")]
+)
+
+(define_insn "madd_split_fused_extended"
+  [(set (match_operand:DI 0 "register_operand" "=&r,r")
+     (sign_extend:DI
+      (plus:SI
+	(mult:SI (match_operand:SI 1 "register_operand" "r,r")
+		 (match_operand:SI 2 "register_operand" "r,r"))
+	(match_operand:SI 3 "register_operand" "r,?0"))))
+    (clobber (match_scratch:SI 4 "=&r,&r"))]
+  "TARGET_ARCV_RHX100
+   && (TARGET_ZMMUL || TARGET_MUL)"
+  {
+     if (REGNO (operands[0]) == REGNO (operands[3]))
+       {
+	 return "mulw\t%4,%1,%2\n\taddw\t%4,%3,%4\n\tmv\t%0,%4";
+       }
+     else
+       {
+	 return "mulw\t%0,%1,%2\n\taddw\t%0,%0,%3";
+       }
+  }
+  [(set_attr "type" "imul_fused")]
+)
+
+(define_insn "*zero_extract_fused"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_operand 2 "const_int_operand")
+			 (match_operand 3 "const_int_operand")))]
+  "TARGET_ARCV_RHX100 && !TARGET_64BIT
+     && (INTVAL (operands[2]) > 1 || !TARGET_ZBS)"
+  {
+     int amount = INTVAL (operands[2]);
+     int end = INTVAL (operands[3]) + amount;
+     operands[2] = GEN_INT (BITS_PER_WORD - end);
+     operands[3] = GEN_INT (BITS_PER_WORD - amount);
+     return "slli\t%0,%1,%2\n\tsrli\t%0,%0,%3";
+  }
+  [(set_attr "type" "alu_fused")]
+)


All of these patterns used to be a defined_insn_and_split. In case we can't get rid of them, let's try to go back to define_insn_and_split (check the downstream commit history) and see what the performance looks like.

If we revert madd_split_fused1 back to a define_insn_and_split we get 0.898% improvement.

I ran embench before and after the revert to define_insn_and_split.
There were some regressions and improvements but the numbers were mostly stable except for the matmul benchmark.
Biggest regression was edn with a 2% drop.
Largest improvement was matmult with a 12% improvements. So I think we can keep this change.

madd_split_fused_extended also still needs to be converted to a define_insn_and_split.

madd_split_fused_extended also still needs to be converted to a define_insn_and_split.

Reverted in: 191282c

Signed-off-by: Luis Silva <luiss@synopsys.com>

This patch adds an improvement of 0.898%. Signed-off-by: Luis Silva <luiss@synopsys.com>

This reverts commit d479345.

Signed-off-by: Luis Silva <luiss@synopsys.com>

…X-100 series Signed-off-by: Luis Silva <luiss@synopsys.com>

…00 series Signed-off-by: Luis Silva <luiss@synopsys.com>

Signed-off-by: Luis Silva <luiss@synopsys.com>

artemiy-volkov and others added 6 commits November 28, 2025 21:03

RISC-V: Add Synopsys RHX-100 series pipeline description

4c5886d

The Synopsys RHX-100 has a 10-stage, dual-issue, in-order execution pipeline. It has support for instruction fusion, which will be addressed by subsequent patches.

RISC-V: Implement riscv_macro_fusion_pair_p for Synopsys RHX-100 series

4364c6a

RISC-V: Implement TARGET_SCHED_FUSION_PRIORITY for Synopsys RHX-100 s…

4d1d83a

…eries

RISC-V: Implement scheduling for Synopsys RHX-100 series

47ccdf4

RISC-V: Add instruction patterns for 32-bit multiply-add and bit-extr…

86cc974

…axt fusion

MichielDerhaeg commented Nov 28, 2025

View reviewed changes

luismgsilva added 2 commits December 2, 2025 14:43

fixup! RISC-V: Implement scheduling for Synopsys RHX-100 series

73219a4

Signed-off-by: Luis Silva <luiss@synopsys.com>

tmp: arcv: protos.

d479345

Signed-off-by: Luis Silva <luiss@synopsys.com>

luismgsilva force-pushed the michiel/fusion-trunk-3 branch from f61d7aa to d479345 Compare December 9, 2025 10:49

luismgsilva added 8 commits December 11, 2025 07:31

tmp: Revert madd_split_fused1 to define_insn_and_split.

b5d541d

This patch adds an improvement of 0.898%. Signed-off-by: Luis Silva <luiss@synopsys.com>

Revert "tmp: arcv: protos."

632b6e6

This reverts commit d479345.

fixup! RISC-V: Add Synopsys RMX-100 series pipeline description

514d182

Signed-off-by: Luis Silva <luiss@synopsys.com>

fixup! RISC-V: Implement scheduling for Synopsys RHX-100 series

6a7c48d

Signed-off-by: Luis Silva <luiss@synopsys.com>

fixup! RISC-V: Implement TARGET_SCHED_FUSION_PRIORITY for Synopsys RH…

6cf07a1

…X-100 series Signed-off-by: Luis Silva <luiss@synopsys.com>

fixup! RISC-V: Implement riscv_macro_fusion_pair_p for Synopsys RHX-1…

eeff0b1

…00 series Signed-off-by: Luis Silva <luiss@synopsys.com>

fixup! RISC-V: Implement scheduling for Synopsys RHX-100 series

d0ff32d

Signed-off-by: Luis Silva <luiss@synopsys.com>

tmp: Revert gen_madd_split_fused_extended to define_insn_and_split.

191282c

Signed-off-by: Luis Silva <luiss@synopsys.com>

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ARC-V RHX-100 upstream patch series #192

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