Upstream Morello EDK-2 Platform changes for SoC #877
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Marking this PR as draft since this on top of #798, once that is merged I'll rebase this PR on top of it and open this one for review. |
Format all files with uncrustify Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ibcf55dcdc9c158d77540b721b57603adbf671b4d
This patch adds morello capability aware software to boot on Morello platform. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I2126e916dd3717e6f145f911510aa300d6227d88
PlatformLibMem.c file is going to be different for Morello FVP and Morello SoC platforms since the virtual memory mapping is different so the file PlatformLibMem.c is renamed as PlatformLibMemFvp.c and PlatformLib.inf is renamed as PlatformLibFvp.inf. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I562d2873b51dd70e71322849ea046885c2562b77
A custom PCI Segment library is required to handle multiple PCIe segments in Morello, as the base PCI Segment library doesn't allow supporting more than a single PCIe segment. This custom platform-specific PCI Segment Library has been adapted from MdePkg/BasePciSegmentLib. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I68c8e2df76846734d33c6f5201a96eadf30cd4e3
Morello platform requires a custom platform-specific PCI Express library because the native PCI Express Library only allows for a single ECAM config address to be supplied to it. If there is more than one PCIe root port, it expects the ECAM regions for all the root ports to be contiguous. This is not the case with Morello where the two RPs have their ECAM regions mapped to non-contiguous address ranges and reside in separate PCIe segments. This custom plaform-specific PCI Express library, inherited from MdePkg/BasePciExpressLib, routes the ECAM accesses to the appropriate ECAM region based on the PCIe segment number in the incoming PCIe address. Segment 0 is PCIe root complex and segment 1 is CCIX root complex. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I624c0aae87efc23d97b269750b0faeaa3b9549ba
Set PCDs which are required for enabling PCIe and CCIX. Also move the common inf file from FVP specific dsc to common dsc file. The default value in .dec files are for the SoC and the FVP overrides it. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I41a57364828ab9b550ece38fc8a81cfcf03f28a0
Morello has many PcdPcixxx which are defined in gArmTokenSpaceGuid and gEfiMdePkgTokenSpaceGuid, use them instead of creating new PCD. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I79ce195ea64f3b3061e6b9c42bd3319e94c97350
The FVP module parse the NT_FW_CONFIG device tree and pass the parsed data to other PEI modules via gArmMorelloFvpPlatformInfoDescriptorPpiGuid (on FVP) The same data are passed to the DXE-phase via the gArmMorelloPlatformInfoDescriptorGuid Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Iac720cb5d9e7be2c8ed8f5c18130ca237e300e50
Morello SoC platform support has added and also boot flow modified to reflect the new boot flow for both Morello FVP and Morello SoC platforms Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I99a7232d45447087d7fd93626e7d856e637c05e0
Include the module required to enable network stack Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ida56ea90871882451bb21f84713ad0daabc8b6cb
This change is required to add the support for enabling the persistent storage for SoC alone, and by keeping the emulated storage for FVP, since FVP doesn't have a QSPI controller/flash for enabling the persistent storage. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I3827f5b6bb97446e649fb8e1a5dac71cf78788f3
Change the AXI Exapansion peripherals size name for Morello FVP Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Iad09e3bdaffcba06bb7b35c849fd897394824bb9
Add the SMMU, GIC ITS and Timer memory regions to the MMU translation table. SBSA test running at uefi shell access SMMU, GIC ITS, REFCLK CNTRead, AP_REFCLK CNTCL and AP_REFCLK_NS CNTCTL, which leads to synchronous exception because of the missing MMU translations. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I4bd0ac55e5c43af4b9a1c1cc462b93b9d44a4b5e
In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the IPI0 trigger method to "level", which prevented SGI0 to be enabled again *after* a CPU offline/online cycle. This patch fixes the above issue by assigning the correct IRQ ID for the UART. Also, the frequency has been changed to 24MHz since IOFPGA UART1 is used as the Debug UART. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ia9260e1c798eaa4bf5307bfddf17d1e542ae4708
Implement LcdHwLib for the ARM Mali Dxx display controller family for use with LcdGraphicsOutputDxe. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I55d1ba655834c3a84a7c73ab5fa24b52d68ba5f9
The platform GOP frame-buffer must be within the lower 40-bits of the memory space. To guarantee this and make sure that frame-buffer memory is always available we carve out a reservation at the end of the 32-bit DDR mapping. The size of this carve-out is controlled by the PCD gArmMorelloTokenSpaceGuid.PcdPlatformGopBufferSize and a size of 0 means to disable memory reservation for the platform frame-buffer. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I5aa22801e9e54e155347a5fe5bc6f1323f6f8a21
Because the FVP do not have any input drivers in UEFI we do not want to enable the console redirection on it. However, we want the GOP to be made available to the OS (that may have drivers). This is achieved by setting a mode if one has not already been set. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ie74240396b14083b82c174cd49c37ebadf6ba941
The MorelloHwConfigPeim module passes the device tree (HW_CONFIG) from the EL3_FW to the DXE-phase via the gFdtHobGuid HOB. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I78eeb5a69e28ff9ba0bbeffe45d8f61d9476c037
On Morello, the EL3 firmware can optionally supply the Device Tree for the hardware (also called HW_CONFIG). If the EL3 firmware provides one, make sure to expose it. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I8a178b06ca81060ba911e539ff7fbacf876ec4ce
The Morello platform includes two clusters with CPUs each. Add processor container devices for the two clusters and move the existing processor devices into respective processor containers. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I4489ea07b8e650fefb889bf45719aff4ff294fb1
This patch adds the necessary LPI state and method definitions to support cpuidle when the kernel is booted with ACPI enabled. Co-authored-by: Karl Meakin <karl.meakin@arm.com> Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I30e5708c9a93225e52d3c6986d7073ec401e2f60
It includes virutal memory map for Morello SoC platform. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ia904e08828a1d8f6d57ca5039eedb82c78c3d43d
This patch adds PlatformDxe support for Morello SoC platform. It includes the registration of ramdisk device. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ie1f6755f25da1fbba9142dc789095294599ac31d
This patch implements the configuration manager for Morello
SoC platform. It enables support for generating the following
ACPI tables for Morello SoC Platform:
1. FADT
2. DSDT
3. GTDT
4. MADT
5. SPCR
6. DBG2
7. PPTT
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: Ic311580ad5ae4bb346e3117777be59569bfbde9c
This commit adds: - SSDT, MCFG table for PCIe and CCIX RC nodes - IORT nodes bindings for PCIe/CCIX and the associated ITSs and SMMUs in the Configuration Manager. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ib4bb62ef5fd261b1a6750f6c4b106bd36a14385b
Support has been added to parse NT_FW_CONFIG DTB to get the platform information. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I491c66c0cf6fa95795c51ad328aafafe21a2ab1c
SMBIOS provides basic hardware and firmware configuration information through table-driven data structure. This patch adds SMBIOS driver support that allows for installation of multiple SMBIOS types. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I71aae128539c0fab699d197b5cde5a6547539e89
DynamicTablesPkg added support to handle FADT minor revision. This patch passes the platform specific FADT minor version. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I3445e8641a369cc2915e50fbd16712b18cda9e83
This patch adds a function to poll Nor flash memory's status register bit (WIP bit) to wait for an erase/write operation to complete. The polling timeout is set to 1 second. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I50aea1887e78fa2f076da1073ea52d53c7cbca6d
The SMBIOS header for this table was initialised with the wrong table's size, which was 3 bytes greater than the correct value. As a result, the first three characters from the strings, the "ARM" in "ARM LTD" for the chassis manufacturer, are erroneously attributed to the table and so parsers interpret the manufacturer as " LTD". Signed-off-by: Jessica Clarke <jessica.clarke@cl.cam.ac.uk> Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I7bd4d4d5b05d6994ae6d937bcf7ca2b14b36a86b
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ifbd5642fd35470effb216485e6dc80371b62f108
On Morello, the EL3 firmware can optionally supply the Device Tree for the hardware (also called HW_CONFIG). If the EL3 firmware provides one, make sure to expose it. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I86fd14f1f4e1537291c24c5cae2069b25233cab5
Remove ArmPlatformLib from [LibraryClasses] as it is not used and on Morello that library introduces a DEPEX on gArmMorelloSocPlatformInfoDescriptorPpiGuid which never can be fulfilled during the DXE-phase. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ifc319cdefe69343881a9e7695b360d670d2df99e
LogoDxe.inf includes a BMP logo in the EFI file, the driver decodes the BMP file and provide the image via EDKII_PLATFORM_LOGO_PROTOCOL. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I3b829ce935a04f9e3f86002b0be9a5b73fc4d737
If the SMCCC_ARCH_SOC_ID is supported, fetch the SoC ID from it else it is populated from the MIDR register. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I97082a9cf73e95d2224708c3c6778f81cf61b7b3
Populate the Processor Version string of SMBIOS TYPE4 table based on SoC revision obtained from the SoC ID. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ifb7df2175441b2ffafdbb70cb1299e7f76c82a9c
PCDs are added for CoreSight devices on Morello. DSDT and configuration manager are updated to include the devices. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I4683b6e924bb33e92b7d99b9985694dd85b5d0a9
Inline with commit a3c8989 (Platform AARCH64: Move PrePeiCore users to Sec.inf) use Sec.inf Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I96bbb7b0a14f12c8529d5c2bb65244f131ca50f7
With the version of NorFlashDxe defined in ArmPlatformPkg getting deprecated, switching usage of NorFlashPlatformLib defined in ArmPlatformPkg to it's local definition in Platform/ARM. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I26a21aa46c432558da88a3a53c1316f37b65cc10
The IORT Specification E.d updates the IORT table revision to 5. To reflect this change the IORT header file has been updated to rename the EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro which was at Rev 0 to EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00. Therefore, update the usage of EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro in the Configuration Manager for Morello SoC to EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I94b2b7d11385b0a071e5b7f139c930e3074e07d0
In ACPI, multiple instances of an IP block in the same namespace may be differentiated by the Unique Identifier (_UID) object. This must be unique across all devices with a common _HID or _CID. _UID objects are added for all CoreSight devices with multiple instances in Morello, so that each device can be uniquely identified. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ia7cebf217015ce1afc68902763179ec6b3f5b086
The Morello platform includes two clusters with CPUs each. Add processor container devices for the two clusters and move the existing processor devices into respective processor containers. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Iaaaa4ade7d794df1a3185366106f2e1e2350899f
This patch adds the necessary LPI state and method definitions to support cpuidle when the kernel is booted with ACPI enabled. Co-authored-by: Karl Meakin <karl.meakin@arm.com> Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I649f5f7c76082001a1d68a962bbbd899b5f06aa9
SMBIOS version previously defaulted to 3.3 as specified in MdeModulePkg.dec. Morello requires an increase to 3.5 for addition of Type 45 Firmware Inventory Information tables. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I6de678e8a0c7b1ad89c2eb4a38aa4d62757489bb
Add firmware inventory information table support for Morello, parsing version information for EDK II and EDK II platforms. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I5e25724c59398dc7d878a6b2895d73f3dc4f779c
SCP firmware version from NT_FW_CONFIG is used to generate and install a Type45 SMBIOS table for the component. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: Ica619cc049196414b96258aab4f162715cc2dff5
MCC and PCC versions in NT_FW_CONFIG are used to generate and install Type45 SMBIOS tables for each component. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I952302760eacaa2d5d62a4f886f8d51d6049b30f
TF-A version string in NT_FW_CONFIG is used to generate and install a Type 45 SMBIOS table for the component. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I744644b077f5b38b38bf783ea05dd73a14f364d3
Resolves error where version may be displayed as unknown when the mainline flag is set. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I6d7c6db235f7b0a44709672c5b798284d323c0b8
Modification of PcdFirmwareVersionString violates memory permissions when building with GCC. This modification is removed to ensure that permissions are respected. Additional checks are added for memory allocations to avoid potential NULL pointer dereferencing. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I34040fe86404563db185489c730e98c08d1e1c4a
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: I15a181975deb46be5c6eb5accfef220ba2793156
Update the size of virtio devices to 64KB as per FVP reference guide https://developer.arm.com/documentation/102225/latest/ Section: Morello Platform Model notes and limitations Change-Id: I6993258cb5a401cb84fc7a9d327702bde57eedbf
Change-Id: Iac5f9611d7df5385e944979de3f63d9ed4533d07
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This patch: - Describes the _LPI states in the Configuration Manager of the Morello - Add the generator of a new SSDT table describing the CPU topology and its _LPI states - Removes the CPU topology description of the DSDT table Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
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This is the second PR in the Morello upstream effort which is focusing on SoC while the previous PR #798 is focusing on FVP related changes.
edk2-platform repository in morello project is hosted at https://git.morello-project.org/morello/edk2-platforms/-/tree/morello/master which is not regularly synced with upstream master and hence have fallen behind. The idea of the effort is to port the extra patches from the above downstream repo to here.
I have tested this PR for boot to UEFI shell on Morello Hardware.